ADPD144RI datasheet(22/34 Pages) AD

22 / 34 page

ADPD144RI

Data Sheet

Rev. A | Page 22 of 34

MECHANICAL CONSIDERATIONS FOR COVERING

THE ADPD144RI

In some applications, it may be necessary to cover the ADPD144RI

to protect the device from moisture. The ADPD144RI is

designed with this necessity in mind. The unique cross section

of the device, as shown in Figure 11, prevents light from going

directly from the LED to the detector even with a reasonably

thick window. The window thickness must be less than 1 mm.

SAMPLE SETUP FILE SpO2

The following sequence of register writes configures the device

for optimal reading of the SpO2 levels in reflectance mode

using the integrated 660 nm (LED1) and 880 nm (LED2) LED

emitters. In this setup, all four photodiodes are connected to

Channel 3 and Channel 4 for best SNR. Eight LED pulses per

slot and eight samples per average. The optical data rate is set to

100 data reads per second for Time Slot A and Time Slot B.

Unwritten registers are set to their default values at power up and

stay that way unless written to.

Figure 23 shows the reflectance PPG taken when using the

example setup file detailed in Table 12 programmed through

Analog Devices, Inc., Wavetool software available on the

ADPD144RI product page.

Figure 23. Reflectance PPG Taken Using the Example SpO2 Setup File (see

Table 12) Programmed Through Analog Devices Wavetool Software

Table 12. Example SpO2 Setup File

Value

Description

0x10

0x0001

Mode

Set this register to 0001 to write to registers.

0x02

0x0005

INT_IO_CTL

Enables the interrupt drive, low active.

0x11

0x30A9

SLOT_EN

If FIFO full drop package, Time Slot A = sample mode, Time Slot B = sample mode, Time Slot A =

32-bit sum, and Time Slot B = 32-bit sum.

0x12

0x000A

F_SAMPLE

Sample rate = 800 Hz.

0x14

0x0116

PD_LED_SELECT

PD1, PD2, PD3, and PD4 into Channel 3 and Channel 4, Time Slot A and Time Slot B active,

pulse LED2 Time Slot A, and pulse LED1 Time Slot B. See Figure 14.

0x15

0x0330

NUM_AVG

Average samples for Time Slot A = 8, and average samples for Time Slot B = 8.

0x18

0x3FFF

SLOTA_CH1_OFFSET

16,383 not used.

0x19

0x3FFF

SLOTA_CH2_OFFSET

16,383 not used.

0x1A

0x1FF0

SLOTA_CH3_OFFSET

8,176 half scale.

0x1B

0x1FF0

SLOTA_CH4_OFFSET

8,176 half scale.

0x1E

0x3FFF

SLOTB_CH1_OFFSET

16,383 not used.

0x1F

0x3FFF

SLOTB_CH2_OFFSET

16,383 not used.

0x20

0x1FF0

SLOTB_CH3_OFFSET

8,176 half scale.

0x21

0x1FF0

SLOTB_CH4_OFFSET

8,176 half scale.

0x23

0x3005

ILED1_COARSE

Scale 100% and driver current = 100 mA.

0x24

0x3007

ILED2_COARSE

Scale 100% and driver current = 130 mA.

0x25

0x0207

ILED_FINE

LED1 = 593.75 ns and LED2 = 593.75 ns.

0x30

0x0319

SLOTA_LEDMODE

Pulse Offset A = 25 µs and pulse width = 3 µs.

0x31

0x0813

SLOTA_NUMPULSES

Pulse Period A = 19 µs and Pulse Count A = 8.

0x35

0x0319

SLOTB_LEDMODE

Pulse Offset B = 25 µs and pulse width = 3 µs.

0x36

0x0813

SLOTB_NUMPULSES

Pulse Period B = 19 µs and Pulse Count A = 8.

0x39

0x21F3

SLOTA_AFEMODE

Time Slot A AFE fine offset = 593.75 ns (19 × 31.25 ns), AFE offset = 15 µs, and AFE width = 4 µs.

0x3B

0x21F3

SLOTB_AFEMODE

Time Slot A AFE fine offset = 593.75 ns (19 × 31.25 ns), AFE offset = 15 µs, and AFE width = 4 µs.

0x42

0x1C36

SLOTA_GAIN

Time Slot A TIA = 50,000, band-pass filter = 390 kHz/100 kHz, VREF = 1.265 V, and integrator =

200,000/6.33 pF.

0x44

0x1C36

SLOTB_GAIN

Time Slot B TIA = 50,000, band-pass filter = 390 kHz/100 kHz, VREF = 1.265 V, and integrator =

200,000/6.33 pF.

0x4E

0x0040

ADC_TIMING

The ADC clock only pulses during conversion.

0x10

0x0002

Mode

Set this register to 0002 to run the device.

ADPD144RI Datasheet(PDF) 22 Page - Analog Devices

ADPD144RI Datasheet(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL