ADPD144RI datasheet(10/34 Pages) AD

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ADPD144RI

Data Sheet

Rev. A | Page 10 of 34

SAMPLING OPERATION

The ADPD144RI samples bursts of synchronous pulses in two

independent time slots, Time Slot A and Time Slot B, which

occur sequentially within a sample period. The entire signal

path from LED stimulation to data capture and processing is

executed during each time slot. Time Slot A and Time Slot B

feature separate datapaths that can be configured with

independent settings for the LED driver, AFE setup, and the

resulting data. In a typical Sp02 application, the red and IR

emitters are assigned to different time slots, allowing each

wavelength independent calibration.

Each time slot can contain 1 to 255 pulses. The energy from

each pulse is collected, and the total energy minus ambient light

is sampled by the ADC. A burst accumulator sums the pulse

energies into a 20-bit value. The number of pulses in each time

slot is set in the top octet of Register 0x31 for Time Slot A and

discrete sample and the combined Time Slot A and Time Slot B,

when both are used, is considered a sampling period. Flexibility

in pulse number and emitter power allows the designer to

choose the best balance of sampling rate, sensitivity, and power

consumption for the application.

PULSE TIMING

The pulse timing for each time slot is programmed in

Sampling starts with the pulse delay, which is the time from the

acquisition start to the rising edge of the first pulse. Time Slot A

and Time Slot B operate in sequence for every sampling period

in which these slots are both enabled.

To calculate sample timing use the following equation:

Pulse Offset + (Pulse Count × Pulse Period) + Processing Time (1)

where:

Pulse Offset is the delay before the first pulse in each sample.

Pulse Count is the total number of pulses within a time slot.

Pulse Period is the time from the start of one pulse to the start of

the subsequent pulse.

Processing Time is the time for the burst accumulator to sum the

pulse energy and place the data on the internal bus.

The following timing calculations use the configuration detailed

in Table 12.

25 µs, Pulse Width A = 3 µs, Pulse Period A = 19 µs, and

Pulse Count A = 8.

Time Slot A (tA) = 25 µs + 8 × 19 µs + 68 µs = 245 µs

= 25 µs, Pulse Width B = 3 µs, Pulse Period B = 19 µs, and Pulse

count B = 8.

Time Slot B (tB) = 25 µs + 8 × 19 µs + 20 µs = 197 µs

Processing time for Time Slot A (t1) is fixed at 68 µs and

Time Slot B (t2) is fixed at 20 µs.

Note that nA is the number of pulses for Time Slot A, and nB is

the number of pulses for Time Slot B.

The minimum sleep time (tSLEEP_MIN) between samples is 200 µs

but can be longer depending on the fSAMPLE, see Register 0x12,

Bits[15:0].

TIME SLOT B

SLEEP

TIME SLOT A

SAMPLE PERIOD = 1/

fSAMPLE

nA PULSES

nB PULSES

SAMPLE

PULSE PERIOD = AFE MEASURE WINDOW

LED PULSE WIDTH

TIME SLOT A

TIME SLOT B

AVERAGE TIME SLOT A = NA SAMPLES

TIME SLOT A

PULSE DELAY

SLEEP

SAMPLE

Figure 12. Time Slot Timing Diagram

Table 9. Recommended AFE and LED Timing Configuration

Address

Recommended Setting

SLOTA_LEDMODE

0x30

0x0319

SLOTB_LEDMODE

0x35

0x0319

SLOTA_AFEMODE

0x39

0x21F3

SLOTB_AFEMODE

0x3B

0x21F3

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