ADPD144RI datasheet(31/34 Pages) AD

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Data Sheet

ADPD144RI

Rev. A | Page 31 of 34

Address

Data

Bit

Default

Access

Name

Description

[8:6]

0x0

R/W

SLOTB_FIFO_MODE

Time Slot B FIFO data format.

0: no data to FIFO.

1: 16-bit sum of all 4 channels.

2: 32-bit sum of all 4 channels.

4: 4 channels of 16-bit sample data.

6: 4 channels of 32-bit extended sample.

Others: reserved.

The selected Time Slot B data is saved in the FIFO. Available only if

Time Slot A has the same averaging factor, NSAMPLE (Register 0x15,

Bits[10:8] = Bits[6:4]), or if Time Slot A is not saving data to the FIFO

(Register 0x11, Bits[4:2] = 0).

0x0

R/W

SLOTB_EN

Time Slot B enable. 1: enables Time Slot B.

[4:2]

0x0

R/W

SLOTA_FIFO_MODE

Time Slot A FIFO data format.

0: no data to FIFO.

1: 16-bit sum of all 4 channels.

2: 32-bit sum of all 4 channels.

4: 4 channels of 16-bit sample data.

6: 4 channels of 32-bit extended sample.

Others: reserved.

0x0

R/W

Reserved

Write 0x0.

0x0

R/W

SLOTA_EN

Time Slot A enable. 1: enables Time Slot A.

0x38

0x0

R/W

Reserved

0x0

R/W

EXT_SYNC_ENA

Write 0x1 when EXT_SYNC_SEL (Register 0x4F, Bit 2) is set to 1.

Otherwise, write 0x0.

[13:0]

0x0

R/W

Reserved

0x4B

[15:8]

0x26

R/W

Reserved

0x0

R/W

CLK32K_EN

Sample clock power-up. Enables the data sample clock.

0x0: clock disabled.

0x1: normal operation.

0x0

R/W

Reserved

[5:0]

0x12

R/W

CLK32K_ADJUST

Data sampling (32 kHz) clock frequency adjust. This register calibrates

the sample frequency of the device to achieve high precision on the

data rate as defined in Register 0x12. Adjusts the sample master 32 kHz

clock by 0.6 kHz per LSB. For a 100 Hz sample rate as defined in

larger value produces a lower frequency. See the Clocks and Timing

Calibration section for more information regarding clock adjustment.

00 0000: maximum frequency.

10 0010: typical center frequency.

11 1111: minimum frequency.

0x4D

[15:8]

0x42

R/W

Reserved

[7:0]

0x5E

R/W

CLK32M_ADJUST

Internal timing (32 MHz) clock frequency adjust. This register calibrates

the internal clock of the device to achieve precisely timed LED pulses.

Adjusts the 32 MHz clock by 109 kHz per LSB. See the Clocks and

Timing Calibration section for more information on clock adjustment.

0000 0000: minimum frequency.

0101 1110: default frequency.

1111 1111: maximum frequency.

0x4E

[15:0]

0x0060

R/W

ADC_TIMING

Write 0x0040.

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