ADPD144RI datasheet(19/34 Pages) AD

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Data Sheet

ADPD144RI

Rev. A | Page 19 of 34

Calibrating the 32 MHz Clock

The 32 MHz clock calibrates items associated with fine timing

within a sample period, such as LED pulse width and spacing.

Only calibrate the 32 MHz clock after the 32 kHz clock is

calibrated. To calibrate the 32 MHz clock, take the following

steps:

1. Write 0x1 to Register 0x5F, Bit 0 (FIFO_ACCESS_ENA).

2. Enable the CLK_RATIO calculation by writing 0x1 to

counts the number of 32 MHz clock cycles in two cycles of the

32 kHz clock. With this function enabled, this cycle value is

stored in Register 0x0A, Bits[11:0], and nominally this ratio is

0x7D0.

3. Calculate the 32 MHz clock error as follows:

Clock Error = 32 MHz × (1 − CLK_RATIO/2000)

(5)

4. Adjust the frequency by setting Bits[7:0] in Register 0x4D

per the following equation:

CLK32M_ADJUST = Clock Error/109 kHz

(6)

5. Write 0x0 to Register 0x50, Bit 5 (CLK32M_CAL_EN) to

reset the CLK_RATIO function.

Repeat Step 2 through Step 5 until the desired accuracy is achieved.

Write 0x0 to Register 0x5F, Bit 0 and set the INT pin back to the

mode desired for normal operation.

DETERMINING CVLED

The synchronous excitation of the ADPD144RI LED emitters is

provided by pulsed current sinks. A pulsed signal greatly reduces

the average power requirement of the VLED supply but requires that

the VLED supply provide a high dynamic current to satisfy the pulse

current. Output impedance, PCB trace resistance and parasitic

inductances affect the ability to supply the instantaneous current

necessary to maintain the forward voltage across the LED. The

CVLED capacitor provides a local, low impedance current source that

reduces the dynamic requirements on the VLED supply.

A properly sized CVLED typically has a sufficient storage capacity

to prevent the forward voltage on the LED from dropping less

than the minimum voltage required for the maximum pulse

current. To calculate the recommended minimum value for the

CVLED, use the following equation:

– (

+ 0.2)

LED_PULSE

F_PEAK

VLED

LED_MIN

F_PEAK

(7)

where:

CVLED is the minimum size of capacitor in Farads.

tLED_PULSE is the LED pulse width.

IF_PEAK is the maximum forward-bias current on the LED used in

operating the device.

VLED_MIN is the voltage from the VLED supply under IF_PEAK.

VF_PEAK is the maximum forward-bias voltage required on the

LED to achieve IF_PEAK.

Figure 8 shows the LED forward-bias voltage drop vs. the LED

driver current settings for the integrated LED emitters. To

determine the CVLED value, determine the peak forward-bias

voltage, VF_PEAK of the LED in operation. For example, the

660 nm LED requires a forward voltage (VF) of approximately

3.5 V to drive a forward current (IF) of 150 mA. If 150 mA is the

highest power used in the design, VF_PEAK = 3.5 V.

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

300

250

200

150

100

LED DRIVER CURRENT SETTING (mA)

880nm

660nm

Figure 21. LED Forward-Bias Voltage Drop vs. LED Driver Current Setting for

the Integrated LED Emitters

The numerator of the CVLED equation sets up the total discharge

amount in coulombs from the bypass capacitor to satisfy a

single programmed LED pulse at the maximum current. The

denominator represents the difference between the lowest

voltage from the VLED supply and the LED required voltage plus

the 0.2 V compliance necessary for the driver.

For a typical ADPD144RI example, assume that the lowest value

for the VLED supply is 4.0 V and that the peak current is 150 mA for

the 660 nm LED (LED1). The minimum value for CVLED is then

equal to 1.5 µF.

CVLED = (3 × 10−6 × 0.150)/(4.0 − (3.5 + 0.2)) = 1.5 µF

(8)

In addition, consider the effect of VLED output impedance and

parasitic impedance from the traces. As shown in Equation 8, as

the supply voltage drops close to the minimum required anode

voltage, the demands on CVLED become greater, forcing the

capacitor value higher. Therefore, adding margin on CVLED is

strongly recommended. It is also recommended to place CVLED

close to the VLED pin to optimize optical pulse quality.

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