ADPD144RI datasheet(12/34 Pages) AD

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ADPD144RI

Data Sheet

Rev. A | Page 12 of 34

STATE MACHINE OPERATION

During each time slot, the ADPD144RI operates according to a

state machine. The state machine operates in the following

sequence (see Figure 15).

STANDBY

ULTRA LOW POWER MODE

NO DATA COLLECTION

ALL REGISTER VALUES ARE RETAINED.

PROGRAM

SAFE MODE FOR PROGRAMMING REGISTERS

NO DATA COLLECTION

DEVICE IS FULLY POWERED IN THIS MODE.

SAMPLE

LEDs ARE PULSED AND PHOTODIODES ARE SAMPLED

STANDARD DATA COLLECTION

DEVICE POWER IS CYCLED BY INTERNAL STATE MACHINE.

Figure 15. State Machine Operation Flowchart

The ADPD144RI operates in one of three modes: standby,

program, and sample.

Standby mode is a power saving mode in which no data collection

occurs. All register values are retained in this mode. To place

the device in standby mode, write 0x0 to Register 0x10, Bits[1:0].

The device powers up in standby mode.

Program mode is used for programming registers. Always cycle

the ADPD144RI through program mode when writing registers

or changing modes. Because no power cycling occurs in this mode,

the device may consume higher current in program mode than

in normal operation. To place the device in program mode,

write 0x1 to Register 0x10, Bits[1:0].

In normal operation (sample mode), the ADPD144RI pulses

light and collects data. Power consumption in this mode

depends on the pulse count and data rate. To place the device in

sample mode, write 0x2 to Register 0x10, Bits[1:0].

SAMPLE MODE OPERATION AND DATA FLOW

In sample mode, the ADPD144RI follows a specific pattern

that is set up by the state machine. This pattern is shown in the

corresponding data flow diagram in Figure 16. The pattern is as

follows:

1. LED pulse and sample. The ADPD144RI pulses an LED

emitter. The response of a photodiode or photodiodes to the

reflected light is measured by the ADPD144RI. Each data

sample is constructed from the sum of n individual pulses,

where nPULSE is user configurable between 1 and 255.

2. Intersample averaging. If desired, the logic can average

N-samples, from 2 to 128 in powers of 2, to produce output

data. New output data is saved to the output registers every

N samples.

3. Data read. The host processor reads the converted results

from the data register or the FIFO.

4. Repeat. The sequence has a few different loops that enable

different types of averaging while keeping both time slots

close in time relative to each other.

SAMPLE 1: TIME SLOT B

16 BITS

[14 + LOG2(nA)] BITS

UP TO 20 BITS

[14 + LOG2(nA × NA)] BITS

UP TO 27 BITS

[14 + LOG2(nB × NB)] BITS

UP TO 27 BITS

TIME SLOT B

TIME SLOT A

NOTES

1. nA AND nB

2. NA AND NB

16 BITS

[14 + LOG2(nB)] BITS

UP TO 20 BITS

16-BIT CLIP

IF VAL = (216 – 1)

VAL = VAL

ELSE VAL = 216 – 1

16-BIT CLIP

IF VAL = (216 – 1)

VAL = VAL

ELSE VAL = 216 – 1

ADC OFFSET

[14 + LOG 2(nA)] BITS

UP TO 22 BITS

SAMPLE 1: TIME SLOT A

SAMPLE NB: TIME SLOT B

SAMPLE NA: TIME SLOT A

14 BITS

14-BIT

ADC

0x11[13]

32-BITDATA

REGISTERS

16-BIT

DATA

REGISTERS

FIFO

nA = PULSE COUNT A

NA = SAMPLE COUNT A

(AVERAGE)

NB = SAMPLE COUNT B

(AVERAGE)

= NUMBER OF SAMPLES AVERAGED FOR TIME SLOT A OR B

= NUMBER OF PULSES IN TIME SLOT A OR B

20-BIT CLIP

IF VAL = (220 – 1)

VAL = VAL

ELSE VAL = 220 – 1

Figure 16. ADPD144RI Data Flow

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