ADPD144RI datasheet(14/34 Pages) AD

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ADPD144RI

Data Sheet

Rev. A | Page 14 of 34

External LEDs

External LEDs can be driven for applications beyond SpO2 or

for use in transmission PPG. Leaving the VLED pin unconnected

effectively disables the integrated LED emitters on the ADPD144RI.

The external LED anodes require connection to an external LED

supply, VXLED. The cathodes of the external LEDs are connected to

the LEDX1 and LEDX2 pins.

CVLED

LED1

TO HOST

PROCESSOR

LED2

SCL

SDA

INT

VREF

LEDX1

ADPD144RI

LEDX2

1µF

VXLED

0.1µF

VDD = 1.8 V

NOTES

1. NC = NO CONNECT.

Figure 17. Connection of External LEDs

The ADPD144RI LED drivers are pulsed current sinks, which

allows programming of the LED pulse currents without concern

for LED supply voltage or LED technology as long as the LEDX1

and LEDX2 voltages stay within the working envelope of the

current sinks, 0.2 V > 3.6 V above LGND. Below 0.2 V, the LED

driver performance cannot be guaranteed. The LED drivers

have an absolute maximum voltage rating of 3.6 V. Any voltage

exposure over this rating affects the reliability of the device

operation and, in certain circumstances, causes the device to

completely cease proper operation.

The voltage that is presented to the LEDX1 and LEDX2 pins

when using the external LEDs is the VXLED supply voltage minus

the forward voltage drop across the diode plus the voltage drop

of any resistance in line with the LED. The operating forward

voltage for an LED depends on the type and technology of the

LED and varies only a small amount over the operating range of

the LED. Forward voltage is typically 1.3 V for an 880 nm LED1

and 1.8 V for a 660 nm LED2, while shorter wavelengths

operate at higher forward voltages. Voltage drop across any

resistance in series with the LED varies with instantaneous

current and must be considered when calculating the voltage at

LEDX1 and LEDX2. Even though the average current through

the LED is small, the pulsed current is high enough to be

affected by series resistance, and care in the layout to reduce

series inductance and resistance in the circuit path between the

VXLED supply through the external LED and into the LEDX1 and

LEDX2 driver pins is recommended.

Multiple Sample Averaging and Accumulation

The ADPD144RI digital processing block can provide sample

accumulation and averaging to increase signal resolution and

improve signal noise shaping.

As shown in Figure 16, pulses acquired by the AFE (nA or nB)

are summed and clipped to 20-bit samples at the output of the

burst accumulator. The effective gain and dynamic range of the

AFE can be further extended to 27 bits by summing multiple

samples (NA or NB) in the sample accumulator at the expense of

the effective sampling rate.

The 27-bit values are padded up to 32-bit words and can be read

out directly by using the 32-bit output registers or the 32-bit

FIFO configuration. New data is written to the registers at the

rate of fSAMPLE/N every Nth sample. The 16-bit registers remain

active during 32-bit sample accumulation. Data from the

sample accumulator is decimated and clipped to prevent

overrun of the 16-bit output registers. Sample averaging can be

used to integrate the noise while maintaining 16-bit resolution.

Writing 0 to Register 0x11, Bit 13 places the digital decimation

filter into the datapath of the 32-bit registers. This provides

20-bit average data to the 32-bit registers. When using the

averaging feature, samples can be averaged by powers of 2. The

user can select from 2, 4, 8 … up to 128 samples to be averaged.

Data Read

The host processor reads output data from the ADPD144RI, via

the I2C protocol, from the data registers or from the FIFO. New

output data is made available every N samples, where N is the user

configured averaging factor. The averaging factors for Time Slot A

and Time Slot B are configurable independently of each other. If

the time slots are the same, both time slots can be configured to

save data to the FIFO. If the two averaging factors are different,

only one time slot can save data to the FIFO. Data from the

other time slot can be read from the output registers.

The data read operations are described in more detail in the

Reading Data section.

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