ADPD144RI datasheet(16/34 Pages) AD

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ADPD144RI

Data Sheet

Rev. A | Page 16 of 34

APPLICATIONS INFORMATION

TYPICAL CONNECTION DIAGRAM

Figure 19 illustrates the recommended connection diagram for

the ADPD144RI. The 1.8 V I2C communication lines, SCL and

SDA, along with the INT line, connect to a system microprocessor

or sensor hub. A level translator may be necessary if the I2C

lines from the microprocessor are not 1.8 V logic.

Provide the 1.8 V supply, tied to VDD1 and VDD2. Use

standard regulator circuits according to the peak current

requirements specified in Table 1 and calculated in the

Calculating the Total Power Consumption section.

For best noise performance, connect AGND, DGND, and LGND

together at a large conductive surface such as a ground plane,

ground pour, or large ground trace.

ADPD144RI

LGND

SDA

DGND

AGND

VDD1

VREF

SCL

INT

VDD2

LEDX2

LEDX1

VLED

1µF

SDA

VLED

SCL

INT

0.1µF

CVLED

1.8V

Figure 19. Connection Diagram

LAND PATTERN

Figure 20 shows the recommended PCB footprint (land

pattern). Table 7 and Figure 3 provide the recommended

soldering profile.

0.905mm

0.7mm

0.45mm

2.0mm

Figure 20. Land Pattern

RECOMMENDED START-UP SEQUENCE

The ADPD144RI does not require a particular power-up

sequence. The device powers up in standby mode (Register 0x10 =

0x0000).

From standby mode, to begin measurement, initiate the

ADPD144RI as follows:

Write 0x0001 to Register 0x10 to force the device into

program mode.

Registers must be written while the device is in program

mode. Registers may be written in any order.

Set SAMPLE_CLK, Register 0x4B, Bit 7 (CLK32K_EN) to

start the sample clock (32 kHz clock). This step must be

done only once after power-up of the device. However,

writing to the bit more than once does not cause a

problem.

Write 0x0002 to Register 0x10 to force the device to

normal operation.

The ADPD144RI is now sampling and data can be read from

the output register and/or FIFO depending on set

configuration.

To place the ADPD144RI into standby mode:

Write 0x0001 to Register 0x10 to force the device into

program mode.

If desired, write registers in any order while the device is in

program mode.

Write 0x00FF to Register 0x00 to clear all interrupts. If

desired, clear the FIFO as well by setting

DATA_ACCESS_CTL, Register 0x5F, Bit 0

(FIFO_ACCESS_ENA) and writing 0x80FF to Register

0x00. Reset Register 0x5F, Bit 0 back to 0 when this step is

complete.

Write 0x0000 to Register 0x10 to force the device into

standby mode.

This step is optional. For absolute minimum standby

power consumption, disable the 32 kHz clock by setting

SAMPLE_CLK, Register 0x4B, Bit 7 (CLK32K_EN) to 0.

This must be written when the device is in standby mode

(Register 0x10 = 0x0).

The ADPD144RI is now in standby mode.

Warning: if 0 is written to Register 0x4B, Bit 7 (CLK32K_EN)

while in program mode or normal mode, the device is unable to

transition into any other mode, including standby mode. As a

result, the power consumption in what appears to be standby

mode is greatly elevated. Due to the low current draw of the

32 kHz clock while in operation, it is recommended, from an

ease of use perspective, to keep the 32 kHz clock running after

the clock is turned on.

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