Data Sheet

ADPD144RI

Rev. A | Page 15 of 34

(data) pin and the SCL (clock) pin. All internal registers are

and User Manual, Rev. 05—9 October 2012, available from NXP

Semiconductors. The ADPD144RI supports fast mode (400 kbps)

data transfer. Register read and write operations are supported, as

operations. Single word and multiword read operations are

supported. For a single register read, the host sends a no

acknowledge (NACK) after the second data byte is read and

a new register address is needed for each access.

For multiword operations, each pair of data bytes is followed by

an acknowledge (ACK) from the host until the last byte of the

last word is read. The host indicates the last read word by

sending a NACK. When reading from the FIFO (Register 0x60),

the data is automatically advanced to the next word in the FIFO,

and the space is freed. When reading from other registers, the

register address is automatically advanced to the next register,

allowing the user to read without readdressing each register and

thereby reducing the amount of overhead required to read

multiple registers. This auto-increment does not apply to the

register that precedes the FIFO, Register 0x5F, or the last data

register, Register 0x7F.

All register writes are single word only and require 16 bits

(one word) of data.

Term

Description

SCL

Serial clock.

SDA

Serial address and data.

Master

The device that initiates a transfer, generates clock signals, and terminates a transfer.

Slave

The device addressed by a master. The ADPD144RI operates as a slave device.

Start (S)

A high to low transition on the SDA line while SCL is high. All transactions begin with a start condition.

Start (Sr)

A repeated start condition.

Stop (P)

A low to high transition on the SDA line while SCL is high. A stop condition terminates all transactions.

ACK

During the acknowledge (ACK) or no acknowledge (NACK) clock pulse, the SDA line is pulled low and remains low.

NACK

During the ACK or NACK clock pulse, the SDA line remains high.

Slave Address

After a start (S), a 7-bit slave address is sent, which is followed by a data direction bit (read or write).

Read (R)

A 1 indicates a request for data.

Write (W)

A 0 indicates a transmission.

NOTES

1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.

MASTER START

SLAVE ADDRESS + WRITE

REGISTER ADDRESS

SLAVE

ACK

ACK

ACK

ACK

MASTER START

Sr

SLAVE ADDRESS + WRITE

REGISTER ADDRESS

ACK/NACK

STOP

SLAVE

ACK

ACK

DATA[7:0]

REGISTER WRITE

DATA[15:8]

REGISTER READ

SLAVE ADDRESS + READ

ACK

DATA[7:0]

DATA[15:8]

STOP

ACK

DATA TRANSFERRED

n (DATA[15:8]+ACK+DATA[7:0] + ACK/NACK)

MASTER START

Sr

SLAVE ADDRESS + WRITE

REGISTER ADDRESS

NACK

STOP

SLAVE

ACK

ACK

DATA[7:0]

REGISTER READ

SLAVE ADDRESS + READ

ACK

DATA[15:8]

ACK

I2C WRITE

I2C SINGLE WORD READ MODE

I2C MULTIWORD READ MODE