LT8551 datasheet(10/32 Pages) AD

10 / 32 page

LT8551

Rev 0

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PIN FUNCTIONS

REG (Pin 3): Output of REG LDO. Power supply for gate

drivers. Decouple this pin to ground with a minimum

4.7µF low ESR ceramic capacitor. Connect this pin to the

external PMOS drain side.

BG1, BG2, BG3, BG4 (Pins 11, 10, 2, 1): Bottom Gate

Driver Output. These pins drive the gates of the bottom

N-channel MOSFETs. Voltage swing at these pins is from

ground to REG.

BGBUF (Pin 12): Logic Output Pin. This pin is pulled up

to REG when BGSH is at logic high, and it is pulled down

to ground when BGSH is at logic low. For a slave LT8551,

leave this pin floating. See the Applications Information

section for more information.

TGBUF (Pin 13): Logic Output Pin. For a master LT8551,

this pin is pulled up to REG voltage when (TGSH–TGSL)

is at logic high, and it is pulled down to ground when

(TGSH–TGSL) is at logic low. For a slave LT8551, leave

this pin floating. See the Applications Information section

for more information.

BST1, BST2, BST3, BST4 (Pins 14, 7, 6, 52):Boosted

Floating Driver Supply. The (+) terminal of the boost-strap

capacitor is connected to this pin. This pin swings from a

diode voltage drop below REG up to VOUT + REG.

TG1, TG2, TG3, TG4 (Pins 15, 8, 5, 51): Top Gate Driver

Output. This is the output of a floating driver with a volt-

age swing equal to REG superimposed on the switch node

voltage.

SW1, SW2, SW3, SW4 (Pins 16, 9, 4, 50): Switch Node.

Voltage swing at these pins is from a diode voltage drop

below ground to VOUT.

TGSR (Pin 17): The Rail of Primary Channel Top Gate

Sense Circuit. For a master LT8551, connect this pin to

the primary channel top gate driver’s boost node. This pin,

combined with TGSH, TGSL pins, is to sense the primary

channel top MOSFET’s state. For a slave LT8551, connect

this pin to REG.

TGSH (Pin 18): Input of Primary Channel Top Gate Sense

Circuit. For a master LT8551, connect this pin to the pri-

mary channel top MOSFET’s gate. This pin, combined

with TGSR, TGSL pins, is to sense the primary channel

top MOSFET’s state. For a slave LT8551, connect this pin

to the master LT8551’s TGBUF pin.

TGSL (Pin 19): Lower Rail of Primary Channel Top Gate

Sense Circuit. For a master LT8551, connect this pin to

the primary channel top MOSFET’s source. This pin, com-

bined with TGSR, TGSH pins, is to sense the primary

channel top MOSFET’s state. For a slave LT8551, connect

this pin to ground.

CLK1, CLK2 (Pins 21, 20): Clock Pin. These two pins

are used to synchronize the primary channel to all other

channels. See the Applications Information section for

more information.

BGSH (Pin 22): Logic Input of Primary Channel Bottom

Gate Sense Circuit. For a master LT8551, connect this

pin to the primary channel bottom MOSFET’s gate. This

pin is to sense the primary channel bottom MOSFET’s

state. For a slave LT8551, connect this pin to the master

LT8551’s BGBUF pin.

SYNC (Pin 23): To synchronize the switching frequency

to an outside clock, simply drive this pin with a clock. The

high voltage level of the clock must exceed 1.2V, and the

low level must be less than 0.8V. Drive this pin to less

than 0.8V to revert to the internal free-running clock. See

the Typical Applications section.

PHS1, PHS2 (Pins 25, 24): Phase Selection Pin. These

pins, combined with PHS3 and RT/MS, set the switching

frequency and the phase of each channel. PHS1 and PHS2

are three-level input pins, they can be floated, set to REG

or ground. When the PHS1/PHS2 is floating, add a 1nF

cap from PHS1/PHS2to ground. See the Operation section

for more information.

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