LT8551 datasheet(22/32 Pages) AD

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LT8551

Rev 0

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APPLICATIONS INFORMATION

Table 3. Recommended Values for Gate Sensing Filters

Primary’s

INTVCC

Voltage (V)

R1 = R3 = R5

(kΩ)

R2 = R4 = R6

(kΩ)

(nF)

(Ω)

6.0

4.7

1.0

6.5

3.3

1.0

7.0

2.2

1.0

7.5

1.0

0.68

8.0

1.0

0.68

9.0

1.0

0.68

9.5

9.1

1.0

0.68

1.0

In addition, R1–R6 should be in the range of kΩ or higher

to reduce the quiescent current. And in order to sense the

primary top gate state correctly during the SW node tran-

sition, the C1 and C2 capacitance within 1nF to 100nF and

CH>4.7nF are recommended. These dividers and filters

should be close to the master LT8551 in the PCB layout.

Power Stage Components Selection Guideline

The power stage components include the input and output

capacitor, inductor, power N-channel MOSFETs and the

optional Schottky diode. Each LT8551’s expanded chan-

nel always adopts the exact same power stage compo-

nents as the primary controller. The following sections

offer a brief guideline for the power device selection. Refer

to the primary controller’s data sheet for more detailed

information.

Inductor Selection

For high efficiency, choose an inductor with low core loss,

such as ferrite. Also the inductor should have low DC

resistance to reduce the I2R losses, and must be able to

handle the peak inductor current without saturating. To

minimize radiated noise, use a toroid, pot core or shielded

bobbin inductor.

The inductor selection is interrelated with maximum aver-

age load current and inductor current ripple, which means

the inductor must have a rating greater than its peak oper-

ating current to prevent saturation and the inductance

must be large enough to decrease the current ripple so

that the maximum average current can be fed to the load

due to the limited peak inductor current.

Power MOSFET, Schottky Diode (Optional) Selection

and Efficiency Considerations.

Critical parameters for power MOSFET selection include

the on-resistance (RDS(ON)), Miller capacitance (CMILLER),

BVDSS (i.e. drain-source breakdown voltage) and maxi-

mum output current, all those parameters can be found

on the manufacture’s data sheet. The gate drive voltage

is set by the REG LDO (5V, typical value), consequently

logic level (5V) MOSFET must be used for the LT8551.

It’s very important to consider power dissipation when

selecting the power MOSFETs. The most efficient cir-

cuit will use MOSFETs that dissipate the least amount of

power. Power dissipation must be limited to avoid over-

heating that might damage the device. When the LT8551

operates in continuous mode, the duty cycles for the top

and bottom MOSFETs are given by:

Main Switch Duty Cycle =

VOUT – VIN

VOUT

Synchronous Switch Duty Cycle =

VIN

VOUT

If the maximum output current is IOUT(MAX) the MOSFET

power dissipation at maximum output current is given by:

PMAIN=

VOUT – VIN

(

)VOUT

VIN2

•IOUT MAX

(

)

2 • 1+δ

(

)

•RDS(ON) +k • VOUT3 •

IOUT MAX

(

)

VIN

•CMILLER • f

PSYNC=

VIN

VOUT

•IOUT MAX

(

)

2 • 1+δ

(

)•RDS(ON)

Both MOSFETs have I2R losses while the bottom N-channel

equation includes an additional term for transition losses,

which are highest at low input voltages. For high VIN the

high current efficiency generally improves with larger

MOSFETs, while for low VIN the transition losses rapidly

increase to the point that the use of a higher RDS(ON) device

with lower CMILLER actually provides higher efficiency. The

synchronous MOSFET losses are greatest at high input

voltage when the bottom switch duty factor is low.

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