LT8551 datasheet(25/32 Pages) AD

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LT8551

Rev 0

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APPLICATIONS INFORMATION

Therefore, R2 may be used to scale the voltage across the

sense terminals when the DCR is greater than the target

sense resistance. With the ability to program the current

limit through ILIM pin, R2 may be optional. C is usually

selected in the range of 0.01μF to 0.47μF. This forces

R1||R2 to be around kΩ range.

For DCR current sensing, the sense lines should also

run close together to a Kelvin connection underneath the

inductor as shown in Figure 17. To prevent noise from

coupling into the sensitive small-signal nodes, resistor

R1 should be placed close to the inductor, while R2 and

C are placed close to the LT8551 as shown in Figure 16b.

Figure 17.

TO SENSE FILTER

NEXT TO ISPx/ISNx

INDUCTOR OR RSENSE

VOUT

VIN

8551 F17

Sense Lines Placement for DCR Sensing

or Resistor Sensing

Thermal Shutdown

If the die junction temperature reaches approximately

165°C, the LT8551 will go into thermal shutdown. All the

power switches will be turned off. For a master LT8551,

the ENOUT pin will be pulled down to ground so that it

will shut down all the switching activity of the system. The

LT8551 will be re-enabled when the die temperature has

dropped by about 5°C (nominal).

Efficiency Considerations

The percent efficiency of LT8551 is equal to the output

power divided by the input power times 100%. It is often

useful to analyze individual losses to determine what is

limiting the efficiency and which change would lead to

the most improvement. Percentage efficiency can be

expressed as:

% Efficiency = 100% – (L1 + L2 + L3 + …)

Where L1, L2, etc. are the individual losses as a percent-

age of input power. Although all dissipative elements in

the circuit produce power losses, several sources usually

account for most of the losses in LT8551 circuits:

1. I2R losses. I2R losses arise from the DC resistance of

the MOSFETs, inductor and current sense resistor. It

is the majority of power losses at high input/output

current. In continuous mode, the average input cur-

rent flows through the inductor and RSENSE, but is

chopped between the top and bottom MOSFETs. If the

two MOSFETs have approximately the same RDS(ON),

then the resistance of one MOSFET can simply be

summed with the inductor’s DCR, RSENSE and the

board traces to obtain I2R losses.

2. Transition loss. This loss mostly arises from the brief

amount of the time the bottom MOSFET spends in the

saturation (Miller) region during the switching node

transitions. It depends on the output voltage, load

current, driver strength and MOSFET capacitance. The

transition can be significant at high output voltages

and low input voltage or high switching frequency.

3. REG current. This is the sum of MOSFETs driver

and REG control currents. The MOSFET driver cur-

rent results from switching the gate capacitance

of the power MOSFETs. Each time a MOSFET gate

is switched from low to high then to low again, a

packet of charge dQ moves from REG to ground. The

resulting dQ/dt is a current out of REG that is typically

much larger than control circuit current. In continu-

ous mode, IGATECHG = f • [QT + QB], where QT and QB

are the gate charges of the top and bottom MOSFETs.

As mentioned in the REG LDO and VCC Power Section,

powering up the REG LDO with lower power supply

will not only improve efficiency, especially for high

input voltage application, but also alleviate the ther-

mal stress for the LDO’s P-channel MOSFET.

4. Body diode conduction loss. During the dead time,

the loss in the top/bottom MOSFET is IL • VF, where

VF is around 0.7V. At higher switching frequency, the

dead time becomes a good percentage of switching

cycle and causes the efficiency to drop.

Other hidden losses, such as copper trace and internal bat-

tery resistances, can account for an additional efficiency

degradation in portable systems. It is very important to

include these system-level losses during the design phase.

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