LT8551 datasheet(19/32 Pages) AD

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LT8551

Rev 0

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APPLICATIONS INFORMATION

REG LDO and VCC Power

The REG LDO supplies the power for the gate drivers and

output stages of CLK1, CLK2, TGBUF and BGBUF. Once the

SHDN pin is higher than 1.15V, REG will be regulated to

4V (typical), (REGSNS – IAMPN) voltage, or 5.25V (typi-

cal) from VIN, depending on whether (REGSNS – IAMPN)

is lower than 4V, or higher than 4V but lower than 5.25V,

or higher than 5.25V respectively, as shown in Figure 11.

The REG pin must be bypassed to power ground with an

X5R or X7R ceramic capacitor of at least 4.7μF placed

close to the REG pin.

Figure 11.

(REGSNS – IAMPN) VOLTAGE (V)

5.25

8551 F11

REG Voltage vs REGSNS Voltage

VCC is the power supply for most of the internal circuitry

and it’s connected to REG through an external filter (RF,

CF) to filter the switching noise in REG, as shown in

Figure 12, the filter should be placed close to the VCC pin,

typical value of RF = 1Ω, CF = 1μF is recommended. The

internal UVLO comparator disables the LT8551’s switch-

ing activity when VCC is lower than 3.55V (typical).

Primary INTVCC Sensing

The primary controller gate driver’s power supply is

INTVCC, as shown in Figure 12. The primary INTVCC volt-

age is filtered and then sensed by the differential unity

gain amplifier A5 in Figure 12, and buffered to REGS_INT

as the reference voltage of the REG LDO. Notice that the

(–) of A5 is connected to IAMPN. As has been discussed

in the Primary Controller’s Inductor Current Sensing

section, both the master LT8551’s IAMPN and the slave

LT8551’s IAMPN are connected to the master LT8551’s

local ground. Since the master’s local ground and the

primary controller’s local ground may have small voltage

difference, this can introduce a small error. To minimize

this error, the master LT8551 should be placed close to

the primary controller.

Figure 12.

10nF

8551 F12

PRIMARY

CONTROLLER

LT8551

IAMPN

REGSNS

INTVCC

VIN

REGIS

REGDRV

REG

VCC

CLP

–

2.2µF

10µF

REGS_INT

CURRENT

LIMIT

*VBIAS

*LOWER VOLTAGE (VBIAS) CAN BE USED FOR VIN PIN TO REDUCE THERMAL

STRESS INSTEAD OF USING THE SUPPLY FOR THE POWER STAGE

REG LDO Configuration

REG LDO Current Limit and External Power PMOS

Selection

Overcurrent protection circuitry limits the maximum cur-

rent drawn from the REG LDO. When the VCC voltage is

below 3.3V during start-up or an overload condition, the

typical current limit is about 110mA. When the REG volt-

age is higher than 3.55V, the current limit depends on the

VIN voltage as shown in Figure 13. If the VIN voltage is

lower than 13.6V or higher than 30V, the current limit is

about 220mA or 100mA respectively. If the VIN voltage is

between 13.6V and 30V, the current limit is inversely pro-

portional to the VIN voltage to limit the maximum power

dissipation in the external power PMOS. The power dis-

sipation in the external PMOS can be calculated by:

P = (VBIAS – REG) • ILDO

Where VBIAS (VIN pin voltage) is the chip power supply

for the LT8551, ILDO is the current drawn from the REG

LDO for a specific application. Use the following formula

to calculate the junction temperature of the PMOS and

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