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C161 Datasheet(PDF) 37 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 37 Page - Infineon Technologies AG |
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37 / 400 page ![]() &3, 0HPRU\ 2UJDQL]DWLRQ User’s Manual 3-1 1999-08 3 Memory Organization The memory space of the C161PI is configured in a “Von Neumann” architecture. This means that code and data are accessed within the same linear address space. All of the physically separated memory areas, including internal ROM/Flash/OTP (where integrated), internal RAM, the internal Special Function Register Areas (SFRs and ESFRs), the address areas for integrated XBUS peripherals and external memory are mapped into one common address space. The C161PI provides a total addressable memory space of 16 MBytes. This address space is arranged as 256 segments of 64 KBytes each, and each segment is again subdivided into four data pages of 16 KBytes each (see figure below). Figure 3-1 Address Space Overview 254...129 255 00’0000 H 0 127 128 64 4 3 2 1 FF’FFFF H 80’0000 H Total Address Space 01’FFFF H 16 MByte, Segments 255...0 00’0000 H 01’FFFF H Segments 1 and 0 01’0000 H Internal ROM Area 64 + 64 KByte 01’8000 H 126...65 63 5 9 8 7 6 11 10 62...12 40’0000 H 0A’FFFF H 08’0000 H 255...2 Data Page 3 Alternate ROM Area Data Page 2 04’FFFF H |
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