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C161 Datasheet(PDF) 17 Page - Infineon Technologies AG |
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C161 Datasheet(HTML) 17 Page - Infineon Technologies AG |
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17 / 400 page ![]() &3, $UFKLWHFWXUDO2YHUYLHZ User’s Manual 2-1 1999-08 2 Architectural Overview The architecture of the C161PI combines the advantages of both RISC and CISC processors in a very well-balanced way. The sum of the features which are combined result in a high performance microcontroller, which is the right choice not only for today’s applications, but also for future engineering challenges. The C161PI not only integrates a powerful CPU core and a set of peripheral units into one chip, but also connects the units in a very efficient way. One of the four buses used concurrently on the C161PI is the XBUS, an internal representation of the external bus interface. This bus provides a standardized method of integrating application-specific peripherals to produce derivates of the standard C161PI. Figure 2-1 C161PI Functional Block Diagram XRAM / CAN CPU Core Internal RAM ROM Area XBUS Module I 2C Bus Module Interrupt Controller PEC WDT OSC PORT0 PORT1 Port 4 ADC GPT1 SSC ASC GPT2 RTC Port 3 Ext. Ctrl Port 6 Port 5 Bus XRAM Port 2 |
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