NCP5331 datasheet(14/38 Pages) ONSEMI

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NCP5331

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APPLICATIONS INFORMATION

Overview

The NCP5331 dc/dc controller utilizes an Enhanced V2

topology to meet requirements of low voltage, high current

loads with fast transient requirements. Transient response

has been improved and voltage jitter virtually eliminated by

including an internal PWM ramp, connecting fast-feedback

from VCORE directly to the internal PWM comparator, and

precise routing and grounding inside the controller.

Advanced features such as adjustable power-good delay,

programmable

overcurrent

shutdown

time,

superior

overvoltage protection (OVP), and differential remote

voltage sensing make it easy to obtain AMD certification.

An innovative overvoltage protection (OVP) scheme

safeguards the CPU during extreme situations including

power up with a shorted upper MOSFET, shorting of an

upper MOSFET during normal operation, and loss of the

voltage feedback signal, COREFB+. The NCP5331

provides a “fully integrated solution” to simplify design,

minimize circuit board area, and reduce overall system cost.

Two advantages of a multiphase converter over a

single-phase converter are current sharing and increased

apparent output frequency. Current sharing allows the

designer to use less inductance in each phase than would be

required in a single-phase converter. The smaller inductor

produces larger ripple currents but the total per phase power

dissipation is reduced because the rms current is lower.

Transient response is improved because the control loop will

measure and adjust the current faster in a smaller output

inductor. Increased apparent output frequency is desirable

because the off-time and the ripple voltage of the two-phase

converter will be less than that of a single-phase converter.

Fixed Frequency Multiphase Control

In a multiphase converter, multiple converters are

connected in parallel and are switched on at different times.

This reduces output current from the individual converters

and increases the apparent ripple frequency. Because several

converters are connected in parallel, output current can ramp

up or down faster than a single converter (with the same

value output inductor) and heat is spread among multiple

components.

The NCP5331 controller uses a two-phase, fixed

frequency, Enhanced V2 architecture to measure and control

currents in individual phases. Each phase is delayed 180

from the previous phase. Normally, GHx (x = 1 or 2)

transitions to a high voltage at the beginning of each

oscillator cycle. Inductor current ramps up until the

combination of the current sense signal, the internal ramp

and the output voltage ripple trip the PWM comparator and

bring GHx low. Once GHx goes low, it will remain low until

the beginning of the next oscillator cycle. While GHx is

high, the Enhanced V2 loop will respond to line and load

variations (i.e. the upper gate on-time will be increased or

reduced as required). On the other hand, once GHx is low,

the loop can not respond until the beginning of the next

PWM cycle. Therefore, constant frequency Enhanced V2

will typically respond to disturbances within the off-time of

the converter.

The Enhanced V2 architecture measures and adjusts the

output current in each phase. An additional input, CSx (x =

1 or 2), for inductor current information has been added to the

V2 loop for each phase as shown in Figure 14. The triangular

inductor current is measured differentially across RS,

amplified by CSA and summed with the Channel Startup

Offset, the Internal Ramp, and the Output Voltage at the

noninverting input of the PWM comparator. The purpose of

the Internal Ramp is to compensate for propagation delays in

the NCP5331. This provides greater design flexibility by

allowing smaller external ramps, lower minimum pulse

widths, higher frequency operation, and PWM duty cycles

above 50% without external slope compensation. As the sum

of the inductor current and the internal ramp increase, the

voltage on the positive pin of the PWM comparator rises and

terminates the PWM cycle. If the inductor starts a cycle

Figure 14. Enhanced V2 Control Employing Resistive Current Sensing and Additional Internal Ramp

SWNODE

RLx

RSx

CSx

CSA

COn

CSREF

VOUT

(VCORE)

“Fast-Feedback”

Connection

PWM

COMP

To F/F

Reset

Channel

Start-Up

Offset

Error

Amp

DAC

Out

VFB

COMP

Internal Ramp

x = 1 or 2

- +

VFFB

NCP5331 Datasheet(PDF) 14 Page - ON Semiconductor

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