NCP5331 datasheet(31/38 Pages) ONSEMI

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NCP5331

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the inductor’s resistance increase due to current heating and

ambient temperature rise. Also, depending on the current

sense points, the circuit board may add additional resistance.

In general, the temperature coefficient of copper is +0.393%

per

°C. If using a current sense resistor (RSENSE), the ILIM

pin voltage should be set based on the maximum value of the

sense resistor. To set the level of the ILIM pin,

VILIM + (IOUT,LIM ) DILo 2) @ R @ GILIM

(34)

where

IOUT,LIM is the current limit threshold of the converter,

∆ILo/2

is half the inductor ripple current,

is either (RLMAX + RPCB) or RSENSE,

GILIM

is the current sense to ILIM gain.

For the overcurrent protection to work properly, the

current sense time constant (RC) should be slightly larger

than the RL time constant. If the RC time constant is too fast,

during step load changes the sensed current waveform will

appear larger than the actual inductor current and will

probably trip the current limit at a lower level than expected.

10. Overcurrent Timer

The overcurrent timer sets the time the converter will

allow hiccup mode operation. Given the capacitance from

the COVC pin to GND, the nominal overcurrent time (tOVC)

can be calculated from the following equation.

tOVC + COVC @ (OVCTHRESH * OVCMIN) IOVC (35)

+ COVC @ (3.0 V * 0.25 V) 5.0 mA

+ COVC @ 5.5

105

where

OVCTHRESH is the overcurrent timer’s shutdown

voltage, nominally 3 V,

OVCMIN

is the overcurrent timer’s starting

voltage, nominally 0.25 V,

IOVC

is the charge current supplied to the

capacitor at the COVC pin, nominally

µA.

11. Soft Start Time

The Soft Start time (tSS) can be calculated from

tSS + (VCOMP * RC1 @ ICOMP) @ CC2 ICOMP (36)

where

VCOMP + VCORE @0A ) Channel_Startup_Offset

) Int_Ramp ) GCSA @ Ext_Ramp 2

Ext_Ramp

+ D @ (VIN * VCORE) (RCSx @ CCSx @ fSW)

Int_Ramp

+ 125 mV @ D 0.50

ICOMP

is the COMP source current from the

data sheet,

Int_Ramp

is the internal ramp value at the

corresponding duty cycle,

Ext_Ramp

is the peak-to-peak external

steady-state ramp at 0 A,

GCSA

is the Current Sense Amplifier Gain

(nominally 2.0 V/V),

Startup Offset is typically 0.60V.

12. Power Good Delay Time

The power good timer sets the delay time between when

VCORE exceeds the CPGD comparator’s threshold voltage

and when PGD will actually transition high. The PGD delay

time can be calculated from

tPGD + CPGD @ (PGDTHRESH * PGDMIN) IPGD (37)

+ CPGD @ (3.0 V * 0.25V) IPGD

where

PGDTHRESH is the PGD comparator’s threshold

voltage, nominally 3 V,

PGDMIN

is the PGD timer’s starting voltage,

nominally 0.25 V,

IPGD

is the charge current supplied to the

capacitor at the CPGD pin. This current

is a function of the ROSC resistor

according to IPGD = 0.52 V/ROSC.

Design Example

Typical Design Requirements:

VIN = 12.0 Vdc

VCORE = 1.20 Vdc (nominal)

VOUT,RIPPLE < 20 mVPP max

VID Range: 0.800 Vdc - 1.550 Vdc

IO,MAX = 52 A at full-load

IOUT,LIM = 72 Adc

dIIN/dt = 0.50 A/µs max

fSW = 200 kHz

η = 80% min at full-load

TA,MAX = 55°C

TJ,MAX = 120°C

tSS = 6.0 ms (Soft Start time)

tOVC = 120 ms (Overcurrent time)

tPGD = 6.0 ms (PGD Delay time)

∆VCORE at no-load (static) =

-25 mV from VID setting = 1.225 Vdc

∆VCORE at full-load (static) =

–37 mV from VID setting = 1.163 Vdc

∆VCORE transient loading from 3.0 A to 25 A =

-50 mV from VID setting = 1.150 Vdc

1. Output Capacitor Selection

First, choose a low-cost, low-ESR output capacitor such

as the Rubycon 16MBZ1000M10X16: 16 V, 1000

µF,

2.55 ARMS, 19 mΩ, 10 × 16 mm. Calculate the minimum

number of output capacitors.

NOUT,MIN

+ ESR per capacitor @

DIO,MAX

DVO,MAX

+ 19 mW @ 22 A (1.225 V * 1.150 V)

+ 5.6 or 6 capacitors minimum (6000 mF)

(1)

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