NCP5331 datasheet(20/38 Pages) ONSEMI

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NCP5331

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During no load conditions the VDRP pin is at the same

voltage as the VFB pin, so none of the VFB bias current flows

through the VDRP resistor. When output current increases

the VDRP pin increases proportionally and the VDRP pin

current offsets the VFB bias current and causes the output

voltage to decrease.

The response during the first few microseconds of a load

transient are controlled primarily by power stage output

impedance and the ESR and ESL of the output filter. The

transition between fast and slow positioning is controlled by

the total ramp size and the error amp compensation. If the

current signal (external ramp) size is too large or the error

amp too slow there will be a long transition to the final

voltage after a transient. This will be most apparent with

lower capacitance output filters.

Error Amp Compensation, Tuning, and Soft Start

The

transconductance

error

amplifier

requires

capacitance (CC1 + CC2 in the Applications Diagram)

between the COMP pin and GND for two reasons. First, this

capacitance stabilizes the transconductance error amplifier.

Values less than a few nF may cause oscillations of the

COMP voltage and increase the output voltage jitter.

Second, this capacitance sets the soft start and hiccup mode

slopes.

The

internal

error

amplifier

will

source

approximately 30

µA during soft start and hiccup mode. No

switching will occur until the COMP voltage exceeds the

Channel Startup Offset (nominally 0.6 V). If CC2 is set to

0.1

µF the 30 µA from the error amplifier will allow the

output to ramp up or down at approximately 30

µ A/0.1 µF

or 0.3 V/ms or 1.2 V in 4 ms.

The COMP voltage will ramp up to the following value.

VCOMP + VCORE @0A ) Channel_Startup_Offset

) Int_Ramp ) GCSA @ Ext_Ramp 2

The COMP pin will disable the converter when pulled

below the COMP Discharge Threshold (nominally 0.27 V).

The RC network between the COMP pin and the soft start

capacitor (RC1, CC1) allows the COMP voltage to slew

quickly during transient loading of the converter. Without

this network the error amplifier would have to drive the large

soft start capacitor (CC2) directly, which would drastically

limit the slew rate of the COMP voltage. The RC1/CC1

network allows the COMP voltage to undergo a step change

of approximately RC1 ⋅ ICOMP.

The capacitor (CA1) between the COMP pin and the error

amplifier’s inverting input (the VFB pin) and the parallel

combination of the resistors RF1 and RDRP determine the

bandwidth of the error amplifier. The gain of the error

amplifier crosses 0 dB at a high enough frequency to give a

quick transient response, but well below the switching

frequency to minimize ripple and noise on the COMP pin.

A capacitor in parallel with the RF1 resistor (CF1) adds a zero

to boost phase near the crossover frequency to improve loop

stability.

Figure 26. Power Good Delay Operation

NOTE:

The PGD timer insures that PGD will transition high

when VCORE is in regulation.

Setting up and tuning the error amplifier is a three step

process. First, the no-load and full-load adaptive voltage

positioning (AVP) are set using RF1 and RDRP, respectively.

Second, the current sense time constant and error amplifier

gain are adjusted with RSx and CA1 while monitoring

VCORE during transient loading. Lastly, the peak-to-peak

voltage ripple on the COMP pin is examined when the

converter is fully loaded to insure low output voltage jitter.

The exact details of this process are covered in the Design

Procedure section.

Undervoltage Lockout (UVLO)

The controller has undervoltage lockout comparators

monitoring two pins. One, intended for the logic and

low- side drivers, is connected to the VCCL pin with an 8.5 V

turn-on and 6.15 V turn-off threshold. A second, for the

high side drivers, is connected to the VCCH pin with an 8.5 V

turn-on and 6.75 V turn-off threshold. A UVLO fault sets

the fault latch which forces switching to stop and the upper

and lower gate drivers produce a logic low (i.e., all the

MOSFETs are turned OFF). Power good (PGD) is pulled

low when UVLO occurs. The overcurrent/overvoltage latch

is reset by the UVLO signal.

Power Good (PGD) Delay Time

When VCORE is less than the power good threshold,

87.5%

⋅ DAC, or greater than 2.0 V the open-collector

power good pin (PGD) will be pulled low by the NCP5331.

When VCORE is in regulation PGD will become high

impedance. An external pull-up resistor is required on PGD.

During soft start, when VCORE reaches the power good

threshold, 87.5%

⋅ DAC, then the “longer” of two timers will

dictate when PGD becomes high impedance. One timer is

internally set to 200

µs and can not be changed. Placing a

capacitor from the CPGD pin to GND sets the second

programmable timer. When VCORE crosses the PGD

threshold, a current source will charge CPGD starting at

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