NCP5331 datasheet(28/38 Pages) ONSEMI

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NCP5331

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For TO-220 and TO-263 packages, standard FR-4

copper clad circuit boards will have approximate thermal

resistances (

θSA) as shown in the following table.

Pad Size

(in2/mm2)

Single-Sided

1 oz. Copper

0.5/323

60-65

°C/W

0.75/484

55-60

°C/W

1.0/645

50-55

°C/W

1.5/968

45-50

°C/W

2.0/1290

38-42

°C/W

2.5/1612

33-37

°C/W

As with any power design, proper laboratory testing

should be performed to insure the design will dissipate the

required power under worst case operating conditions.

Variables considered

during

testing

should

include

maximum ambient temperature, minimum airflow, maximum

input voltage, maximum loading, and component variations

(i.e., worst case MOSFET RDS(on)). Also, the inductors and

capacitors share the MOSFET’s heatsinks and will add heat

and raise the temperature of the circuit board and MOSFET.

For any new design, its advisable to have as much heatsink

area as possible - all too often new designs are found to be

too hot and require redesign to add heatsinking.

6. Adaptive Voltage Positioning

There are two resistors that determine the Adaptive

Voltage Positioning, RF1 and RDRP. RF1 establishes the

no-load “high” voltage position and RDRP determines the

full-load “droop” voltage.

Resistor RF1 is connected between VCORE and the VFB

pin of the controller. At no load, this resistor will conduct the

internal bias current of the VFB pin and develop a voltage

drop from VCORE to the VFB pin. Because the error amplifier

regulates VFB to the DAC setting, the output voltage,

VCORE, will be higher by the amount IBIASVFB ⋅ RF1. This

condition is shown in Figure 33.

To calculate RF1 the designer must specify the no-load

voltage increase above the VID setting (

∆VNO- LOAD) and

determine the VFB bias current. Usually, the no-load voltage

increase is specified in the design guide for the processor

that is available from the manufacturer. The VFB bias current

is determined by the value of the resistor from ROSC to

ground (see Figure TBD for a graph of IBIASVFB versus

ROSC). The value of RF1 can then be calculated.

RF1 + DVNO- LOAD IBIASVFB

(29)

Resistor RDRP is connected between the VDRP and the

VFB pins. At no-load, the VDRP and the VFB pins will both

be at the DAC voltage so this resistor will conduct zero

current. However, at full-load, the voltage at the VDRP pin

will increase proportional to the output inductor’s current

while VFB will still be regulated to the DAC voltage. Current

will be conducted from VDRP to VFB by RDRP. This current

will be large enough to supply the VFB bias current and cause

a voltage drop from VFB to VCORE across RF1 - the

converter’s output voltage will be reduced. This condition is

shown in Figure 34.

To determine the value of RDRP the designer must specify

the full-load voltage reduction from the VID (DAC) setting

(

∆VCORE,FULL- LOAD) and predict the voltage increase at

the VDRP pin at full-load. Usually, the full-load voltage

reduction is specified in the design guide for the processor

that is available from the manufacturer. To predict the

voltage increase at the VDRP pin at full-load (∆VDRP), the

designer must consider the output inductor’s resistance

(RL), the PCB trace resistance between the current sense

points (RPCB), and the controller IC’s gain from the current

sense to the VDRP pin (GVDRP).

DVDRP + IO,MAX @ (RL ) RPCB) @ GVDRP (30)

The value of RDRP can then be calculated.

RDRP +

DVDRP

(IBIASVFB ) DVCORE,FULL- LOAD RF1)

(31)

∆VCORE,FULL- LOAD is the full-load voltage reduction

from the VID (DAC) setting.

∆VCORE,FULL- LOAD is not the

voltage change from the no-load AVP setting.

RS1

CS1

0 A

GVDRP

RS2

CS2

0 A

GVDRP

CSREF

COMP

Error

Amp

VID Setting

IBIASVFB

RDRP

RF1

VDRP = VID

VFB = VID

VCORE

IDRP = 0

IFBK = IBIASVFB

VCORE = VID + IBIASVFB w RF1

Figure 33. AVP Circuitry at No-Load

+ -

NCP5331 Datasheet(PDF) 28 Page - ON Semiconductor

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