DS3172 datasheet(52/232 Pages) DALLAS

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Figure 10-1. Interrupt Structure

GL.ISR.PISRn

PORT.ISR bit

SRL bit

SRIE bit

BLOCK LATCHED

STATUS and

INTERRUPT

ENABLE

REGISTERS

PORT INTERRUPT

STATUS

GLOBAL

INTERRUPT

STATUS REGISTER

and INTERRUPT

ENABLE REGISTER

GL.ISRIE.

PISRIEn

INT

PORT

INTERRUPTS

GLOBAL

INTERRUPTS

Figure 10-1 not only tells the user how to determine which event caused the interrupt, it also tells the user how to

enable a particular interrupt. Each block has a Status Register Interrupt Enable register that must be set in order to

enable an interrupt. The next step is to unmask the interrupt at the port level, on a per port basis. This is controlled

in the Global Interrupt Status Register Interrupt Enable register (GL.ISRIE). Now the device is ready to drive the

INT pin low when a particular status bit gets set.

For example, in order to enable DS3 Out of Frame interrupts on Port 2, the following registers would need to be

written:

Address

Value Written

Note

T3.RSRIE1.OOFIE

0x2BC

0x0002

Unmask OOF interrupt on Port 2

GL.ISRIE.PISRIE2

0x010

0x0020

Unmask Port 2 interrupts

The following status registers bits will be set upon reception of OOF on Port 2:

Address

Value Read

Note

T3.RSRL1.OOFL

0x2B8

0x0002

DS3 Out of Frame on Port 2

PORT.ISR.FMSR

0x250

0x0001

Framer Block Interrupt Active, Port 2

GL.ISR.PISR2

0x010

0x0020

Port 2 Interrupt Active

10.2 Clocks

10.2.1 Line Clock Modes

10.2.1.1 Loop Timing Enabled

When loop timing is enabled (PORT.CR3.LOOPT), the transmit clock source is the same as the receive clock

source. The TCLKIn pins are not used as a clock source. Because loop timing is enabled, the loopback functions

(LLB, PLB and DLB) do not cause the clock sources to switch when they are activated. The transmit and receive

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