DS3172 datasheet(65/232 Pages) DALLAS

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Table 10-12. Global 8 kHz Reference Source Table

GL.CR2.

G8KIS

GL.CR2.

G8KRS[2:0]

Source

000

None, the 8KHZ divider is disabled.

001

Derived from CLAD DS3 clock output or CLKA pin if CLAD

is disabled. (Note: CLAD is disabled after reset)

010

Derived from CLAD E3 clock output or CLKB pin if CLAD is

disabled

011

Derived from CLAD STS-1 clock output or CLKC pin if CLAD

is disabled

100

Port 1 8KREF source selected by P8KRS[1:0]

101

Port 2 8KREF source selected by P8KRS[1:0]

110

Port 3 8KREF source selected by P8KRS[1:0]

111

Port 4 8KREF source selected by P8KRS[1:0]

XXX

GPIO4 pin

Table 10-13 lists the selectable sources for port 8 kHz reference sources.

Table 10-13. Port 8 kHz Reference Source Table

PORT.CR3.P8KRS[1:0]

Source

Undefined

Internal receive framer clock

Internal transmit framer clock

The 8 kHz reference logic tree is shown below.

Figure 10-7. 8KREF Logic

CLOCK DIVIDER

TX CLOCK

RX CLOCK

FRAME MODE

P8KRS

GPIO4

OTHER

PORT

8KREF

DS3 CLK

E3 CLK

CC52 CLK

FROM CLAD

G8KRS[1:0]

G8KRS[2]

G8KREF

GLOBAL 8KREF

PORT 8KREF

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