DS3172 datasheet(8/232 Pages) DALLAS

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DS3171/DS3172/DS3173/DS3174

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LIST OF FIGURES

Figure 1-1. LIU External Connections for a DS3/E3 Port of a DS317x Device ........................................................... 3

Figure 1-2. DS317x Functional Block Diagram ........................................................................................................... 3

Figure 2-1. Four-Port DS3/E3 Line Card ................................................................................................................... 12

Figure 6-1. DS3/E3 SCT Mode.................................................................................................................................. 19

Figure 6-2. DS3/E3 Clear Channel Mode.................................................................................................................. 20

Figure 7-1. HDB3/B3ZS/AMI LIU Mode..................................................................................................................... 22

Figure 7-2. HDB3/B3ZS/AMI Non-LIU Line Interface Mode ...................................................................................... 23

Figure 7-3. UNI Line Interface Mode ......................................................................................................................... 24

Figure 8-1. TX Line IO B3ZS Functional Timing Diagram ......................................................................................... 36

Figure 8-2. TX Line IO HDB3 Functional Timing Diagram ........................................................................................ 37

Figure 8-3. RX Line IO B3ZS Functional Timing Diagram......................................................................................... 37

Figure 8-4. RX Line IO HDB3 Functional Timing Diagram ........................................................................................ 38

Figure 8-5. TX Line IO UNI Functional Timing Diagram............................................................................................ 38

Figure 8-6. RX Line IO UNI Functional Timing Diagram ........................................................................................... 39

Figure 8-7. DS3 Framing Receive Overhead Port Timing......................................................................................... 39

Figure 8-8. E3 G.751 Framing Receive Overhead Port Timing ................................................................................ 39

Figure 8-9. E3 G.832 Framing Receive Overhead Port Timing ................................................................................ 39

Figure 8-10. DS3 Framing Transmit Overhead Port Timing...................................................................................... 40

Figure 8-11. E3 G.751 Framing Transmit Overhead Port Timing ............................................................................. 40

Figure 8-12. E3 G.832 Framing Transmit Overhead Port Timing ............................................................................. 40

Figure 8-13. DS3 SCT Mode Transmit Serial Interface Pin Timing........................................................................... 41

Figure 8-14. E3 G.751 SCT Mode Transmit Serial Interface Pin Timing .................................................................. 41

Figure 8-15. E3 G.832 SCT Mode Transmit Serial Interface Pin Timing .................................................................. 41

Figure 8-16. DS3 SCT Mode Receive Serial Interface Pin Timing............................................................................ 42

Figure 8-17. E3 G.751 SCT Mode Receive Serial Interface Pin Timing ................................................................... 42

Figure 8-18. E3 G.832 SCT Mode Receive Serial Interface Pin Timing ................................................................... 42

Figure 8-19. 16-Bit Mode Write.................................................................................................................................. 43

Figure 8-20. 16-Bit Mode Read ................................................................................................................................. 43

Figure 8-21. 8-Bit Mode Write.................................................................................................................................... 44

Figure 8-22. 8-Bit Mode Read ................................................................................................................................... 44

Figure 8-23. 16-Bit Mode without Byte Swap ............................................................................................................ 45

Figure 8-24. 16-Bit Mode with Byte Swap ................................................................................................................. 45

Figure 8-25. Clear Status Latched Register on Read................................................................................................ 46

Figure 8-26. Clear Status Latched Register on Write................................................................................................ 46

Figure 8-27. RDY Signal Functional Timing Write..................................................................................................... 47

Figure 8-28. RDY Signal Functional Timing Read..................................................................................................... 47

Figure 10-1. Interrupt Structure ................................................................................................................................. 52

Figure 10-2. Internal TX Clock................................................................................................................................... 55

Figure 10-3. Internal RX Clock .................................................................................................................................. 56

Figure 10-4. Example IO Pin Clock Muxing............................................................................................................... 60

Figure 10-5. Reset Sources....................................................................................................................................... 61

Figure 10-6. CLAD Block ........................................................................................................................................... 63

Figure 10-7. 8KREF Logic ......................................................................................................................................... 65

Figure 10-8. Performance Monitor Update Logic ...................................................................................................... 68

Figure 10-9. Transmit Error Insert Logic.................................................................................................................... 69

Figure 10-10. Loopback Modes ................................................................................................................................. 70

Figure 10-11. ALB Mux .............................................................................................................................................. 70

Figure 10-12. AIS Signal Flow ................................................................................................................................... 73

Figure 10-13. Framer Detailed Block Diagram .......................................................................................................... 78

Figure 10-14. DS3 Frame Format.............................................................................................................................. 80

Figure 10-15. DS3 Subframe Framer State Diagram ................................................................................................ 80

Figure 10-16. DS3 Multiframe Framer State Diagram............................................................................................... 81

Figure 10-17. G.751 E3 Frame Format ..................................................................................................................... 88

Figure 10-18. G.832 E3 Frame Format ..................................................................................................................... 91

Figure 10-19. MA Byte Format .................................................................................................................................. 91

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