DS3172 datasheet(85/232 Pages) DALLAS

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The bit C13 is overwritten with the Far-End Alarm and Control (FEAC) data input from the transmit FEAC controller.

The bits C31, C32, and C33 are all overwritten with the calculated payload parity from the previous DS3 frame.

The bits C41, C42, and C43 are all overwritten with the Far-End Block Error (FEBE) bit. The FEBE bit can be

generated automatically or inserted from a register bit. The FEBE bit source is programmable (automatic or

during the previous frame.

The bits C51, C52, and C53 are overwritten with the path maintenance data link input from the HDLC controller.

Once all of the DS3 overhead bits have been overwritten, the data stream is passed on to error insertion. If frame

generation is disabled, the incoming DS3 signal is passed on to error insertion. Frame generation is programmable

(on or off). Note: P-bit generation may still be performed even if frame generation is disabled.

10.6.5.3 Transmit C-bit DS3 Error Insertion

Error insertion inserts various types of errors into the different DS3 overhead bits. The types of errors that can be

inserted are framing errors, P-bit parity errors, C-bit parity errors, and Far-End Block Error (FEBE) errors.

The framing error insertion mode is programmable (F-bit, M-bit, SEF, or OOMF). An F-bit error is a single subframe

alignment bit (FXY) error. An M-bit error is a single multiframe alignment bit (M1, M2, or M3) error. An SEF error is an

error in all the subframe alignment bits in a subframe (FX1, FX2, FX3, and FX4). An OOMF error is a single multiframe

alignment bit (M1, M2, or M3) error in two consecutive DS3 frames.

A P-bit parity error is generated by is inverting the value of the P-bits (P1 and P2) in a single DS3 frame. P-bit parity

error(s) can be inserted one error at a time, or continuously. The P-bit parity error insertion mode (single or

continuous) is programmable.

A C-bit parity error is generated by is inverting the value of the C31, C32, and C33 bits in a single DS3 frame. C-bit

parity error(s) can be inserted one error at a time, or continuously. The C-bit parity error insertion mode (single or

continuous) is programmable.

A FEBE error is generated by forcing the C41, C42, and C43 bits in a single multiframe to zero. FEBE error(s) can be

inserted one error at a time, or continuously. The FEBE error insertion rate (single or continuous) is programmable.

Each error type (framing, P-bit parity, C-bit parity, or FEBE) has a separate enable. Continuous error insertion

mode inserts errors at every opportunity. Single error insertion mode inserts an error at the next opportunity when

requested. the framing multi-error modes (SEF or OOMF) insert the indicated number of error(s) at the next

opportunities when requested; i.e., a single request will cause multiple errors to be inserted. The requests can be

initiated by a register bit(TSEI) or by the manual error insertion input (TMEI). The error insertion initiation type

(register or input) is programmable. The insertion of each particular error type is individually enabled. Once all error

insertion has been performed, the data stream is passed on to overhead insertion.

10.6.5.4 Transmit C-bit DS3 Overhead Insertion

Overhead insertion can insert any (or all) of the DS3 overhead bits into the DS3 frame. The DS3 overhead bits X1,

X2, P1, P2, MX, FXY, and CXY can be sourced from the transmit overhead interface (TOHCLK, TOH, TOHEN, and

TOHSOF). The P-bits (P1 and P2) and C31, C32, and C33 bits are received as an error mask (modulo 2 addition of

the input bit and the internally generated bit). The DS3 overhead insertion is fully controlled by the transmit

overhead interface. If the transmit overhead data enable signal (TOHEN) is driven high, then the bit on the transmit

overhead signal (TOH) is inserted into the output data stream. Insertion of bits using the TOH signal overwrites

internal overhead insertion.

10.6.5.5 Transmit C-bit DS3 AIS/Idle Generation

C-bit DS3 AIS/Idle generation overwrites the data stream with AIS or an Idle signal. If transmit Idle is enabled, the

data stream payload is forced to a 1100 pattern with two ones immediately following each DS3 overhead bit. M1,

M2, and M3 bits are overwritten with the values zero, one, and zero (010) respectively. FX1, FX2, FX3, and FX4 bits are

overwritten with the values one, zero, zero, and one (1001) respectively. X1 and X2 are overwritten with 11. And,

P1, P2, C31, C32, and C33 are overwritten with the calculated payload parity from the previous output DS3 frame.

If transmit AIS is enabled, the data stream payload is forced to a 1010 pattern with a one immediately following

each DS3 overhead bit. M1, M2, and M3 bits are overwritten with the values zero, one, and zero (010) respectively.

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