DS3172 datasheet(41/232 Pages) DALLAS

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Figure 8-13. DS3 SCT Mode Transmit Serial Interface Pin Timing

TCLKO or

TCLKI

DS3 TSER

DS3 TDEN

TSOFO

DS3 TGCLK

TSOFI

TSER DATA IS OVERWRITTEN WITH OH

10 11 12 13

12345

14 15

Figure 8-14. E3 G.751 SCT Mode Transmit Serial Interface Pin Timing

E3 TSER

E3 TDEN

E3 TGCLK

TCLKO or

TCLKI

TSOFO

TSOFI

TSER DATA IS OVERWRITTEN WITH OH

10 11 12 13

345

14 15

Figure 8-15. E3 G.832 SCT Mode Transmit Serial Interface Pin Timing

E3 TSER

E3 TDEN

E3 TGCLK

TCLKO or

TCLKI

TSOFO

TSER DATA IS OVERWRITTEN WITH OH

TSOFI

10 11 12 13

12345

14 15 16 17 18 19 20

8.3.3.2

DS3/E3 SCT Mode Receive Serial Interface Pin Functional Timing

The RSERn signal has the DS3 or E3 payload as well as the DS3 or E3 overhead bits. The RDENn signal is used

to enable external logic for payload processing and will be high during the DS3 or E3 payload bits and low during

the DS3 or E3 overhead bits. The RGCLKn signal can also be used to clock only the DS3 or E3 payload bits into

external logic since the clock is stopped during the DS3 or E3 overhead bits. The RSOFOn signal marks the first

overhead bit of the DS3 or E3 frame.

Figure 8-16 to Figure 8-18 show the relationship between the SCT receive port pins.

DS3172 Datasheet(PDF) 41 Page - Dallas Semiconductor

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