DS3172 datasheet(72/232 Pages) DALLAS

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be framing errors if a framed mode is enabled. When the DS3 framed AIS signal is initiated or terminated, in

addition to no BPV or CV errors, there should be no framing or P-bit (parity) or CP-bit errors introduced.

The AIS signal generated at the top level will not generate BPV errors but may generate P-bit and CP-bit errors

when the signal is initiated and terminated. The framed DS3 AIS signal will not cause the far end receiver to re-

sync when the signal is initiated, but it may cause a re-sync when terminated if the DS3 frame position in the

framer is changed while the DS3 AIS signal is being generated. A sequence of events can be executed which will

enable the initiation and termination of DS3 AIS or unframed all ones at the top level without any errors introduced.

The sequence will only work when the automatic AIS generation is not enabled. CV and P-bit errors can occur

when AIS is automatically generated and cannot be avoided. This sequence to generate an error free DS# AIS at

the top level is to have the DS3 AIS or unframed all ones signal initiate in the DS3 framer, and a few frames sent

before initiating or terminating the DS3 AIS or unframed all ones at the top level. After the top level AIS signal is

activated, the AIS signal in the framer can be terminated, DLB activated and diagnostic patterns generated. The

DS3 AIS signal generated at the top level will not change frame alignment after starting even if the DS3 frame

position in the framer is changed.

The transmit line AIS generator at the top level can generate AIS signals even when the framer is looped back

using DLB, but not when the line is looped back using LLB. The AIS signal generated in the framer will be looped

back to the receive side when DLB is activated.

The receive framer can detect both unframed all ones AIS and DS3 framed AIS patterns. When in DS3 framing

modes, both framed DS3 AIS and unframed all ones can be detected. In E3 framing modes E3 AIS, which is

unframed all ones, is detected.

The receive payload interface going to the RSERn pin or the BERT logic can have an unframed all ones AIS signal

replacing the receive signal, this is called Payload AIS. The all ones AIS signal is generated from either the DS3/E3

framer or the downstream top level unframed all ones AIS generator. The unframed all ones AIS signal generated

in the framer will be looped back to the transmit side when PLB is activated. The unframed all ones AIS signal

generated at the top level will be sent to the RSERn pin and other receive logic, but not to the transmit side while

PLB is activated. The top level AIS generator is used when a downstream AIS signal is desired while payload loop

back is activated and is enabled by default after rest and must be cleared during configuration. Note that the

downstream AIS circuit in the framer, when a DS3 mode is selected, enforces the OOF to be active for 2.5 ms

before activating when automatic AIS in the framer is enabled. The top level downstream AIS will be generated

with no delay when OOF is detected when automatic AIS at the top level is enabled.

There is no detection of any AIS signal on the transmit payload signal from the TSERn pin or anywhere on the

transmit data path.

The transmit AIS generator at the top level can also be activated with a software bit or automatically when DLB is

activated. The receive AIS generator in the framer can be activated with a software bit, and automatically when

AIS, LOS or OOF are detected. The receive payload AIS generator at the top level can be activated with a software

bit or automatically when LOS, DS3/E3 OOF, LLB or PLB is activated.

DS3172 Datasheet(PDF) 72 Page - Dallas Semiconductor