AD6688 datasheet(40/138 Pages) AD

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AD6688

Data Sheet

Rev. 0 | Page 40 of 138

PROGRAMMING INSTRUCTIONS

Follow this sequence to set up the programmable finite impulse

response (FIR) filter:

1. Enable sample CLK to the device.

2. Configure the mode registers.

a. Set device index to Channel A (I path)

(Register 0x0008 = 0x01).

b. Set I path mode (IMODE) and gain in Register 0x0DF8

and Register 0x0DF9 (see Table 12 and Table 13).

c. Set device index to Channel B (Q path)

(Register 0x0008 = 0x02).

d. Set Q path mode (QMODE) and gain in Register 0x0DF8

and Register 0x0DF9.

3. Wait for at least 5 µs to allow the programmable filter to

power up.

4. Program the I path coefficients to the internal shadow

registers.

a. Set device index to Channel A (I path)

(Register 0x0008 = 0x01).

b. Program the I path X coefficients (XI) in

Table 15).

c. Program the I path Y coefficients (YI) in

Table 15).

d. Program tapped delay in Register 0x0F30 (optional).

5. Program the Q path coefficients to the internal shadow

registers:

a. Set device index to Channel B (Q path)

(Register 0x0008 = 0x02).

b. Set Q path mode and gain in Register 0x0DF8 and

c. Program the Q path X coefficients (XQ) in

Table 15).

d. Program Q path Y coefficients (YQ) in Register 0x0F00

to Register 0x0F7F (see Table 14 and Table 15).

e. Program tapped delay in Register 0x0F30 (see Table 14

and Table 15) (optional).

6. Set the chip transfer bit using one of the following methods

(note that setting the chip transfer bit applies the programmed

shadow coefficients to the filter).

•

Write the chip transfer bit (Register 0x000F = 0x01).

•

GPIO pin.

Configure one of the GPIO pins as the chip

transfer bit in Register 0x0040 to Register 0x0042.

ii.

Toggle the GPIO pin to initiate the chip transfer

(rising edge triggered).

7. Whenever the I or Q path mode register changes in

Table 12. Register 0x0DF8 Definition

Bit(s)

Description

[7:3]

Reserved

[2:0]

Filter mode (IMODE or QMODE)

000: filters bypassed

001: real 24-tap filter (X only)

010: real 48-tap filter (X and Y together)

100: real set of two cascaded 24-tap filters (X then Y

cascaded)

101: full complex filter using four real 24-tap filters for

the A and B channels (opposite channel must also be

set to 101)

110: half complex filter using two real 48-tap filters +

48-tap delay line (X and Y together) (opposite channel

must also be set to 010)

111: real 96-tap filter (XI, YI, XQ, and YQ together)

(opposite channel must be set to 000)

Table 13. Register 0x0DF9 Definition

Bit(s)

Description

Reserved

[6:4]

Y filter gain

110: −12 dB loss

111: −6 dB loss

000: 0 dB gain

001: 6 dB gain

010: 12 dB gain

Reserved

[2:0]

X filter gain

110: −12 dB loss

111: −6 dB loss

000: 0 dB gain

001: 6 dB gain

010: 12 dB gain

Table 14 and Table 15 show the coefficient tables in Register 0x0E00

to Register 0x0F30. All coefficients are Q1.15 format (sign bit + 15

fractional bits).

AD6688 Datasheet(PDF) 40 Page - Analog Devices

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