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AD6688 Datasheet(PDF) 73 Page - Analog Devices |
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AD6688 Datasheet(HTML) 73 Page - Analog Devices |
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73 / 138 page ![]() Data Sheet AD6688 Rev. 0 | Page 73 of 138 fS × 4 MODE The fS × 4 mode adds a special packing mode on top of a JESD204B transmitter/receiver to fix the serial lane rate at four times the sample rate (fS). The JESD204B link settings are L = 8; M = 2; F = 2; S = 5; N' = 12; N = 12; CS = 0; CF = 2; and HD = 1. However, CF = 2 is not supported by the design; therefore, the following link parameters are used along with special packing: L = 8; M = 2; F = 2; S = 4; N' = 16; N = 16; CS = 0; CF = 0; and HD = 0. In fS × 4 mode, five 12-bit ADC samples (along with an extra 4 bits) are packed into four 16-bit JESD204B samples to create a 64-bit frame. The following SPI writes are necessary to place the device in fS × 4 mode: • Register 0x0570 = 0xFE. This setting places the device in M = 2, L = 8, fS × 4 mode. • Register 0x058B = 0x0F. This setting places the device in CS = 0, N' = 16. • Register 0x058F = 0x2F. This setting places the device in Subclass 1 mode, N = 16. The transmit architecture of the fS × 4 mode is shown in Figure 101, and the receive portion is shown in Figure 102. The fS × 4 mode only works in full bandwidth mode (Register 0x0200 = 0x00). ADC1 SAMPLE N (12 BITS) CONVERTER 1 SAMPLE N (16 BITS) CONVERTER 1 SAMPLE N+1 (16 BITS) CONVERTER 1 SAMPLE N+2 (16 BITS) CONVERTER 1 SAMPLE N+3 (16 BITS) S[N][15:0] S[N + 1][15:0] S[N + 2][15:0] S[N + 3][15:0] JESD204B FRAMER + PHY (M = 2; L = 8; S = 4; F = 2; N = 16; N’ = 16; CF = 0; HD = 0) APPLICATION LAYER TRANSPORT, DATA LINK, AND PHY LAYERS 12-BITS AT fS LANE 0 LANE 1 LANE 2 LANE 3 LANE 4 LANE 5 LANE 6 LANE 7 fS × 4 MODE (TRANSMIT) 1/5 RATE EXCHANGE ADC1 SAMPLE N (12 BITS) ADC1 SAMPLE N + 1 (12 BITS) ADC1 SAMPLE N + 2 (12 BITS) ADC1 SAMPLE N + 3 (12 BITS) ADC1 SAMPLE N + 4 (12 BITS) (4 BITS) S[N][11:0], S[N + 1][11:8] (16 BITS) S[N + 1][7:0], S[N + 2][11:4] (16 BITS) S[N + 2][3:0], S[N + 3][11:0] (16 BITS) S[N + 4][11:0], 0000 (16 BITS) ADC0 SAMPLE N (12 BITS) ADC0 CONVERTER 0 SAMPLE N (16 BITS) CONVERTER 0 SAMPLE N + 1 (16 BITS) CONVERTER 0 SAMPLE N + 2 (16 BITS) CONVERTER 0 SAMPLE N + 3 (16 BITS) S[N][15:0] S[N + 1][15:0] S[N + 2][15:0] S[N + 3][15:0] 1/5 RATE EXCHANGE ADC0 SAMPLE N (12 BITS) ADC0 SAMPLE N + 1 (12 BITS) ADC0 SAMPLE N + 2 (12 BITS) ADC0 SAMPLE N + 3 (12 BITS) ADC0 SAMPLE N + 4 (12 BITS) (4 BITS) S[N][11:0], S[N + 1][11:8] (16 BITS) 0000 S[N + 1][7:0], S[N + 2][11:4] (16 BITS) S[N + 2][3:0], S[N + 3][11:0] (16 BITS) S[N + 4][11:0], 0000 (16 BITS) 0000 ADC1 64-BITS AT fS/5 64-BITS AT fS/5 Figure 101. fS × 4 Mode (Transmit) fS × 4 MODE (RECEIVE) APPLICATION LAYER DATA LINK, TRANSPORT, AND PHY LAYERS CUSTOMER APPLICATION S[N][15:0] S[N + 1][15:0] S[N + 2][15:0] S[N + 3][15:0] S[N][15:0] S[N + 1][15:0] S[N + 2][15:0] S[N + 3][15:0] JESD204B FRAMER + PHY (M = 2; L = 8; S = 4; F = 2; N = 16; N’ = 16; CF = 0; HD = 0) LANE 0 LANE 1 LANE 2 LANE 3 LANE 4 LANE 5 LANE 6 LANE 7 CONVERTER 1 SAMPLE N (16 BITS) CONVERTER 1 SAMPLE N + 1 (16 BITS) CONVERTER 1 SAMPLE N + 2 (16 BITS) CONVERTER 1 SAMPLE N + 3 (16 BITS) CONVERTER 0 SAMPLE N (16 BITS) CONVERTER 0 SAMPLE N + 1 (16 BITS) CONVERTER 0 SAMPLE N + 2 (16 BITS) CONVERTER 0 SAMPLE N + 3 (16 BITS) ADC1 SAMPLE N (12 BITS) ADC1 SAMPLE N + 1 (12 BITS) ADC1 SAMPLE N + 2 (12 BITS) ADC1 SAMPLE N + 3 (12 BITS) ADC1 SAMPLE N + 4 (12 BITS) (4 BITS) S[N][11:0], S[N + 1][11:8] (16 BITS) S[N + 1][7:0], S[N + 2][11:4] (16 BITS) S[N + 2][3:0], S[N + 3][11:0] (16 BITS) S[N + 4][11:0], 0000 (16 BITS) ADC0 SAMPLE N (12 BITS) ADC0 SAMPLE N + 1 (12 BITS) ADC0 SAMPLE N + 2 (12 BITS) ADC0 SAMPLE N + 3 (12 BITS) ADC0 SAMPLE N + 4 (12 BITS) (4 BITS) S[N][11:0], S[N + 1][11:8] (16 BITS) S[N + 1][7:0], S[N + 2][11:4] (16 BITS) S[N + 2][3:0], S[N + 3][11:0] (16 BITS) S[N+4][11:0], 0000 (16 BITS) 64-BITS AT fS/5 64-BITS AT fS/5 0000 0000 Figure 102. fS × 4 Mode (Receive) |
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