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Data Sheet

AD6688

Rev. 0 | Page 49 of 138

NCO FTW/POW/MAW/MAB Coherent Mode

For coherent mode, the NCO MAW must be set to zero

(0x0000_0000_0000). In this mode, the NCO FTW can be

calculated by the following equation:

)

mod(

round(

FTW 

(5)

where:

FTW is the 48-bit twos complement number representing the

NCO FTW.

fS is the ADC sampling frequency.

fC is the desired carrier frequency.

mod(x) is a remainder function. For example mod(110,100) =

10 and for negative numbers, mod(–32,10) = –2.

round(x) is a rounding function. For example round(3.6) = 4

and for negative numbers, round(–3.4)= –3.

Note that Equation 5 applies to the aliasing of signals in the

digital domain (that is, aliasing introduced when digitizing

analog signals). The MAW must be set to zero to use coherent

mode. When MAW is zero, the programmable modulus logic is

automatically disabled.

For example, if the ADC sampling frequency (fS) is 3000 MSPS

and the carrier frequency (fC) is 416.667 MHz, then,

A_8E23

0x2EC6_C03

)

3000

)

3000

667

416

mod(

round(



FTW

NCO

The actual carrier frequency can be calculated based on the

following equation:

ACTUAL

FTW





For the previous example, the actual carrier frequency (fC_ACTUAL) is

MHz

416.66699

3000

667

416







ACTUAL

A 48-bit POW is available for each NCO to create a known

phase relationship between multiple chips or individual DDC

channels inside the chip.

While in coherent mode, the FTW and POW registers can be

updated at any time while still maintaining deterministic phase

results in the NCO.

NCO Channel Selection

When configured in coherent mode, only one FTW is required

in the NCO. In this mode, the user can switch to any tuning

frequency without the need to reset the NCO by writing to the

FTW directly. However, for fast switching applications, where

either all FTWs are known beforehand or it is possible to queue

up the next set of FTWs, the NCO contains 16 additional

shadow registers (see Figure 75). These shadow registers are

hereafter referred to as the NCO channels.

Figure 76 shows a simplified block diagram of the NCO channel

selection block. The gray lines in Figure 76 represent SPI

control lines.

Only one NCO channel is active at a time, and NCO channel

selection is controlled either by the CMOS GPIO pins or

through the register map.

Each NCO channel selector supports three different modes, as

described in the following sections.

NCO CHANNEL

SELECTION

NCO CHANNEL SELECTION

COUNTER

GPIO

CMOS

PINS

GPIO

SELECTION

MUX

INC

[0]

NCO

CHANNEL SELECTION

0x0314, 0x0334, 0x0354, 0x0374

NCO CHANNEL MODE

[3:0]

MAP

Figure 76. NCO Channel Selection Block

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