AD6688 datasheet(30/138 Pages) AD

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AD6688

Data Sheet

Rev. 0 | Page 30 of 138

DC OFFSET CALIBRATION

The AD6688 contains a digital filter to remove the dc offset from

the output of the ADC. For ac-coupled applications, this filter

can be enabled by writing 0x86 to Register 0x0701. The filter

computes the average dc signal and it is digitally subtracted

from the ADC output. As a result, the dc offset is improved to

better than 70 dBFS at the output. Since the filter does not

distinguish between the source of dc signals, this feature can be

used when the signal content at dc is not of interest. The filter

corrects dc up to ±512 codes and saturates beyond that.

CLOCK INPUT CONSIDERATIONS

For optimum performance, drive the AD6688 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal is

ac-coupled to the CLK+ and CLK− pins via a transformer or clock

drivers. These pins are biased internally and require no

additional biasing.

Figure 53 shows the differential input return loss curve for the

clock inputs across a frequency range of 100 MHz to 6 GHz.

The reference impedance is 100 Ω.

5.0

–5.0

2.0

1.0

–1.0

FREQUENCY (100MHz TO 6GHz)

–2.0

0.5

–0.5

0.2

–0.2

FREQUENCY = 2.503GHz

SDD11 = 0.313/–173.307

IMPEDANCE = Z0 × (0.524 – j0.042)

FREQUENCY = 2.996GHz

SDD11 = 0.337/169.383

IMPEDANCE = Z0 × (0.499 – j0.070)

FREQUENCY = 3.104GHz

SDD11 = 0.332/165.502

IMPEDANCE = Z0 × (0.508 – j0.095)

FREQUENCY = 6GHz

SDD11 = 0.271/54.790

IMPEDANCE = Z0 × (1.218 – j0.581)

Figure 53. Differential Input Return Loss for the CLK± Inputs

Figure 54 shows a preferred method for clocking the AD6688.

The low jitter clock source is converted from a single-ended

signal to a differential signal using an RF transformer.

ADC

CLK+

CLK–

1:2Z

CLOCK

INPUT

Figure 54. Transformer-Coupled Differential Clock

Another option is to ac couple a differential CML or LVDS

signal to the sample clock input pins, as shown in Figure 55.

CLK+

CLK–

ADC

CLOCK INPUT

ADC

150Ω

100Ω

DIFFERENTIAL

TRACE

LVPECL

DRIVER

Figure 55. Differential LVPECL Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. The AD6688 contains an

internal clock divider and a duty cycle stabilizer (DCS). In the

AD6688, the DCS is enabled by default. In applications where

the clock duty cycle cannot be guaranteed to be 50%, a higher

multiple frequency clock along with the usage of the clock

divider is recommended.

When it is not possible to provide a higher frequency clock, it is

recommended to turn on the DCS using Register 0x011C and

showing the different controls to the AD6688 clock inputs. The

output of the divider offers a 50% duty cycle, high slew rate (fast

edge) clock signal to the internal ADC. See the Memory Map

section for more details on using this feature.

AD6688 Datasheet(PDF) 30 Page - Analog Devices

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