AD6688 datasheet(11/138 Pages) AD

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Data Sheet

AD6688

Rev. 0 | Page 11 of 138

TIMING SPECIFICATIONS

Table 5.

Parameter

Description

Min

Typ

Max

Unit

CLK+ to SYSREF+ TIMING REQUIREMENTS

tSU_SR

Device clock to SYSREF+ setup time

−65

tH_SR

Device clock to SYSREF+ hold time

SPI TIMING REQUIREMENTS

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

Minimum period that SCLK must be in a logic high state

tLOW

Minimum period that SCLK must be in a logic low state

tACCESS

Maximum time delay between falling edge of SCLK and

output data valid for a read operation

tDIS_SDIO

Time required for the SDIO pin to switch from an output to

an input relative to the SCLK rising edge

Timing Diagrams

CLK+

CLK–

SYSREF+

SYSREF–

tSU_SR

tH_SR

Figure 2. SYSREF± Setup and Hold Timing

DON’T CARE

SDIO

SCLK

CSB

tDH

tCLK

tDS

R/W

A14

A13

A12

A11

A10

tLOW

tHIGH

tACCESS

Figure 3. SPI Timing Diagram

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