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SC3200 Datasheet(PDF) 32 Page - Advanced Micro Devices |
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SC3200 Datasheet(HTML) 32 Page - Advanced Micro Devices |
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32 / 447 page ![]() 32 AMD Geode™ SC3200 Processor Data Book Signal Definitions Revision 5.1 F3 RD# O O3/5 VIO --- CLKSEL0 I (PD100) INSTRP Strap (See Table 3-6 on page 58.) F4 AD23 I/O INPCI, OPCI VIO Cycle Multiplexed A23 O OPCI F28 THRM# I INTS VSB --- F29 VSB PWR --- --- --- F30 VSS GND --- --- --- F313, 4 PWRCNT1 O OD14 VSB --- G1 WR# O O3/5 VIO G2 VIO PWR --- --- --- G3 IOW# O O3/5 VIO PMR[21] = 0 and PMR[2] = 0 DOCW# O O3/5 PMR[21] = 0 and PMR[2] = 1 GPIO15 I/O (PU22.5) INTS, O3/ 5 PMR[21] = 1 and PMR[2] = 1 G4 ROMCS# O O3/5 VIO --- BOOT16 I (PD100) INSTRP VIO Strap (See Table 3-6 on page 58.) G28 GPWIO1 I/O (PU100) INTs, TS2/ 14 VSB --- G29 GPWIO2 I/O (PU100) INTS, TS2/14 VSB --- G30 VIO PWR --- --- --- G313, 4 PWRCNT2 O OD14 VSB --- H1 TRDE# O O3/5 VIO PMR[12] = 0 GPIO0 I/O (PU22.5) INTS, O3/ 5 VIO PMR[12] = 1 H2 GPIO1 I/O (PU22.5) INT, O3/5 VIO PMR[23]2 = 0 and PMR[13] = 0 IOCS1# O (PU22.5) O3/5 VIO PMR[23]2 = 0 and PMR[13] = 1 TFTD12 O (PU22.5) O1/4 VIO PMR[23]2 = 1 H3 GPIO20 I/O (PU22.5) INT, O3/5 VIO PMR[23]2 = 0 and PMR[7] = 0 DOCCS# O (PU22.5) O3/5 PMR[23]2 = 0 and PMR[7] = 1 TFTD0 O (PU22.5) O1/4 PMR[23]2 = 1 H4 GPIO19 I/O (PU22.5) INTS, O3/ 5 VIO PMR[9] = 0 and PMR[4] = 0 INTC# I (PU22.5) INTS PMR[9] = 0 and PMR[4] = 1 IOCHRDY I (PU22.5) INTS1 PMR[9] = 1 and PMR[4] = 1 H28 VSBL PWR --- --- --- H29 CLK32 O O2/5 VSB --- Ball No. Signal Name I/O (PU/ PD) Buffer1 Type Power Rail Configuration H30 GPIO11 I/O (PU22.5) INTS, O8/ 8 VIO PMR[18] = 0 and PMR[8] = 0 RI2# I (PU22.5) INTS PMR[18] = 1 and PMR[8] = 0 IRQ15 I (PU22.5) INTS1 PMR[18] = 0 and PMR[8] = 1 H31 SDATA_IN2 I INTS VSB F3BAR0+Memory Offset 08h[21] = 1 J1 HSYNC O O1/4 VIO --- J2 VSYNC O O1/4 VIO --- J3 IRTX O O8/8 VIO PMR[6] = 0 SOUT3 O O8/8 PMR[6] = 1 J4 GPIO17 I/O (PU22.5) INTS, O3/ 5 VIO PMR[23]2 = 0 and PMR[5] = 0 IOCS0# O (PU22.5) O3/5 PMR[23]2 = 0 and PMR[5] = 1 TFTDCK O (PU22.5) O1/4 PMR[23]2 = 1 J28 IRRX1 I INTS VSB PMR[6] = 0 SIN3 I INTS VIO PMR[6] =1 J29 POR# I INTS VIO --- J303 MD0 I/O INT, TS2/5 VIO --- J313 MD1 I/O INT, TS2/5 VIO --- K1 NC --- --- --- --- K2 VSS GND --- --- --- K3 VCORE PWR --- --- --- K4 VSS GND --- --- --- K28 VSS GND --- --- --- K293 MD2 I/O INT, TS2/5 VIO --- K303 MD3 I/O INT, TS2/5 VIO --- K313 MD4 I/O INT, TS2/5 VIO --- L1 VSS GND --- --- --- L2 VSS GND --- --- --- L3 VIO PWR --- --- --- L4 VCORE PWR --- --- --- L28 VCORE PWR --- --- --- L293 MD5 I/O INT, TS2/5 VIO --- L30 VSS GND --- --- --- L313 MD6 I/O INT, TS2/5 VIO --- M1 VIO PWR --- --- --- M2 VIO PWR --- --- --- M3 NC --- --- --- --- M4 VSS GND --- --- --- M28 VSS GND --- --- --- M293 MD7 I/O INT, TS2/5 VIO --- M30 VIO PWR --- --- --- M31 DQM0 O O2/5 VIO --- N1 VIO PWR --- --- --- N2 NC --- --- --- --- Ball No. Signal Name I/O (PU/ PD) Buffer1 Type Power Rail Configuration Table 3-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued) |
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