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SC3200 Datasheet(PDF) 84 Page - Advanced Micro Devices

Part # SC3200
Description  AMD GEODE-TM SC3200 PROCESSOR
PDF  447 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

SC3200 Datasheet(HTML) 84 Page - Advanced Micro Devices

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84
AMD Geode™ SC3200 Processor Data Book
Signal Definitions
Revision 5.1
3.4.18
JTAG Interface Signals
Signal Name
Ball No.
Type
Description
Mux
EBGA
TEPBGA
TCK
AL4
E31
I
JTAG Test Clock. This signal has an inter-
nal weak pull-up resistor.
---
TDI
AK5
F29
I
JTAG Test Data Input. This signal has an
internal weak pull-up resistor.
---
TDO
AH6
E30
O
JTAG Test Data Output
---
TMS
AJ5
F28
I
JTAG Test Mode Select. This signal has an
internal weak pull-up resistor.
---
TRST#
AK4
E29
I
JTAG Test Reset. This signal has an inter-
nal weak pull-up resistor.
For normal JTAG operation, this signal
should be active at power-up.
If the JTAG interface is not being used, this
signal can be tied low.
---
3.4.19
Test and Measurement Interface Signals
Signal Name
Ball No.
Type
Description
Mux
EBGA
TEPBGA
GXCLK
AL16
V30
O
GX Clock. This signal is for internal testing
only. For normal operation either program as
FP_VDD_ON or leave unconnected.
FP_VDD_ON+
TEST3
TEST3
AL16
V30
O
Internal Test Signal. This signal is used for
internal testing only. For normal operation
leave unconnected, unless programmed as
FP_VDD_ON.
FP_VDD_ON+
GXCLK
TEST2
B29
AJ1
O
Internal Test Signals. These signals are
used for internal testing only. For normal
operation, leave unconnected unless pro-
grammed as one of their muxed options.
PLL5B
TEST1
C28
AG4
O
PLL6B
TEST0
D28
AH3
O
PLL2B
GTEST
AL5
F30
I
Global Test. This signal is used for internal
testing only. For normal operation this signal
should be pulled down with 1.5 K
Ω.
---
PLL6B
C28
AG4
I/O
PLL6, PLL5 and PLL2 Bypass. These sig-
nals are used for internal testing only. For
normal operation leave unconnected.
TEST1
PLL5B
B29
AJ1
I/O
TEST2
PLL2B
D28
AH3
I/O
TEST0



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