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SC3200 Datasheet(PDF) 44 Page - Advanced Micro Devices |
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SC3200 Datasheet(HTML) 44 Page - Advanced Micro Devices |
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44 / 447 page ![]() 44 AMD Geode™ SC3200 Processor Data Book Signal Definitions Revision 5.1 B6 AD23 I/O INPCI, OPCI VIO Cycle Multiplexed A23 O OPCI B7 VSS GND --- --- --- B8 RD# O O3/5 VIO --- CLKSEL0 I (PD100) INSTRP Strap (See Table 3- 6 on page 58.) B9 WR# O O3/5 VIO B10 VSS GND --- --- --- B11 VSYNC O O1/4 VIO --- B12 NC --- --- --- --- B13 VIO PWR --- --- --- B14 VSS GND --- --- --- B15 NC --- --- --- --- B16 VIO PWR --- --- --- B175, 2 BUSY/WAIT# I INT VIO PMR[23]3 = 0 and (PMR[27] = 0 and FPCI_MON = 0) TFTD3 O O1/4 PMR[23]3 = 1 and (PMR[27] = 0 and FPCI_MON = 0) F_C/BE1# O O1/4 PMR[23]3 = 0 and (PMR[27] = 1 or FPCI_MON = 1) B185, 2 ACK# I INT VIO PMR[23]3 = 0 and (PMR[27] = 0 and FPCI_MON = 0) TFTDE O O1/4 PMR[23]3 = 1 and (PMR[27] = 0 and FPCI_MON = 0) FPCICLK O O1/4 PMR[23]3 = 0 and (PMR[27] = 1 or FPCI_MON = 1) B19 VIO PWR --- --- --- B205,2 SLIN#/ASTRB# O O14/14 VIO PMR[23]3 = 0 and (PMR[27] = 0 and FPCI_MON = 0) TFTD16 O O1/4 PMR[23]3 = 1 and (PMR[27] = 0 and FPCI_MON = 0) F_IRDY# O O14/14 PMR[23]3 = 0 and (PMR[27] = 1 or FPCI_MON = 1) B215,2 INIT# O O14/14 VIO PMR[23]3 = 0 and (PMR[27] = 0 and FPCI_MON = 0) TFTD5 O O1/4 PMR[23]3 = 1 and (PMR[27] = 0 and FPCI_MON = 0) SMI_O O O14/14 PMR[23]3 = 0 and (PMR[27] = 1 or FPCI_MON = 1) B22 VSS GND --- --- --- B23 NC --- --- --- --- B24 VSS GND --- --- --- Ball No. Signal Name I/O (PU/PD) Buffer1 Type Power Rail Configuration B25 VSS GND --- --- --- B26 NC --- --- --- --- B275 DPOS_PORT2 I/O INUSB, OUSB AVC- CUSB --- B285 DNEG_PORT2 I/O INUSB, OUSB AVC- CUSB --- B29 GPIO10 I/O (PU22.5) INTS, O8/8 VIO PMR[18] = 0 and PMR[8] = 0 DSR2# I (PU22.5) INTS PMR[18] = 1 and PMR[8] = 0 IDE_IORDY1 I (PU22.5) INTS1 PMR[18] = 0 and PMR[8] = 1 SDTEST1 O (PU22.5) O2/5 PMR[18] = 1 and PMR[8] = 1 B30 VSS GND --- --- --- B31 VIO PWR --- --- --- C1 AD26 I/O INPCI, OPCI VIO Cycle Multiplexed D2 I/O INPCI, OPCI C2 AD24 I/O INPCI, OPCI VIO Cycle Multiplexed D0 I/O INPCI, OPCI C3 VIO PWR --- --- --- C4 AD25 I/O INPCI, OPCI VIO Cycle Multiplexed D1 I/O INPCI, OPCI C5 GNT0# O OPCI VIO --- DID0 I (PD100) INSTRP Strap (See Table 3- 6 on page 58.) C6 GNT1# O OPCI VIO --- DID1 I (PD100) INSTRP Strap (See Table 3- 6 on page 58.) C7 VIO PWR --- --- --- C8 ROMCS# O O3/5 VIO --- BOOT16 I (PD100) INSTRP VIO Strap (See Table 3- 6 on page 58.) C9 GPIO19 I/O (PU22.5) INTS, O3/5 VIO PMR[9] = 0 and PMR[4] = 0 INTC# I (PU22.5) INTS PMR[9] = 0 and PMR[4] = 1 IOCHRDY I (PU22.5) INTS1 PMR[9] = 1 and PMR[4] = 1 C10 VIO PWR --- --- --- C11 IRTX O O8/8 VIO PMR[6] = 0 SOUT3 O O8/8 PMR[6] = 1 C12 VSS GND --- --- --- C13 VIO PWR --- --- --- C14 VSS GND --- --- --- Ball No. Signal Name I/O (PU/PD) Buffer1 Type Power Rail Configuration Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) |
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