SC3200 datasheet(65/447 Pages) AMD

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AMD Geode™ SC3200 Processor Data Book

Signal Definitions

Revision 5.1

3.4.2

Memory Interface Signals

Signal Name

Ball No.

Type

Description

Mux

EBGA

TEPBGA

MD[63:0]

See

Table 3-3

on page

38.

See

Table 3-5

on page

54.

I/O

Memory Data Bus. The data bus lines

driven to/from system memory.

---

MA[12:0]

See

Table 3-3

on page

38.

See

Table 3-5

on page

54.

Memory Address Bus. The multiplexed row/

column address lines driven to the system

memory. Supports 256-Mbit SDRAM.

---

BA1

P31

AK14

Bank Address Bits. These bits are used to

select the component bank within the

SDRAM.

---

BA0

P30

AJ13

---

CS1#

AK29

AH27

Chip Selects. These bits are used to select

the module bank within system memory.

Each chip select corresponds to a specific

module bank. If CS# is high, the bank(s) do

not respond to RAS#, CAS#, and WE# until

the bank is selected again.

---

CS0#

P29

AL12

---

RASA#

N31

AK12

Row Address Strobe. RAS#, CAS#, WE#

and CKE are encoded to support the different

SDRAM commands. RASA# is used with

CS[1:0]#.

---

CASA#

N30

AJ12

Column Address Strobe. RAS#, CAS#,

WE# and CKE are encoded to support the

different SDRAM commands. CASA# is used

with CS[1:0]#.

---

WEA#

N29

AH12

Write Enable. RAS#, CAS#, WE# and CKE

are encoded to support the different SDRAM

commands. WEA# is used with CS[1:0]#.

---

DQM7

AJ20

AB31

Data Mask Control Bits. During memory

read cycles, these outputs control whether

SDRAM output buffers are driven on the MD

bus or not. All DQM signals are asserted dur-

ing read cycles.

During memory write cycles, these outputs

control whether or not MD data is written into

SDRAM.

DQM[7:0] connect directly to the [DQM7:0]

pins of each DIMM connector.

---

DQM6

AJ26

AG29

---

DQM5

AC30

AK21

---

DQM4

T28

AL15

---

DQM3

AJ21

AC31

---

DQM2

AL26

AG30

---

DQM1

AF31

AH23

---

DQM0

M31

AL11

---

CKEA

AC28

AL22

Clock Enable. These signals are used to

enter Suspend/power-down mode. CKEA is

used with CS[1:0]#.

If CKE goes low when no read or write cycle

is in progress, the SDRAM enters power-

down mode. To ensure that SDRAM data

remains valid, the self-refresh command is

executed. To exit this mode, and return to

normal operation, drive CKE high.

These signals should have an external pull-

down resistor of 33 K

Ω.

---

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