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SC3200 Datasheet(PDF) 66 Page - Advanced Micro Devices |
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SC3200 Datasheet(HTML) 66 Page - Advanced Micro Devices |
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66 / 447 page ![]() 66 AMD Geode™ SC3200 Processor Data Book Signal Definitions Revision 5.1 SDCLK3 AJ16 V29 O SDRAM Clocks. SDRAM uses these clocks to sample all control, address, and data lines. To ensure that the Suspend mode functions correctly, SDCLK3 and SDCLK1 should be used with CS1#. SDCLK2 and SDCLK0 should be used together with CS0#. --- SDCLK2 AL20 AA28 --- SDCLK1 AH16 W29 --- SDCLK0 AC29 AJ21 --- SDCLK_IN AJ30 AJ27 I SDRAM Clock Input. The SC3200 samples the memory read data on this clock. Works in conjunction with the SDCLK_OUT signal. --- SDCLK_OUT AH28 AK28 O SDRAM Clock Output. This output is routed back to SDCLK_IN. The board designer should vary the length of the board trace to control skew between SDCLK_IN and SDCLK. --- 3.4.2 Memory Interface Signals (Continued) Signal Name Ball No. Type Description Mux EBGA TEPBGA 3.4.3 Video Port Interface Signals Signal Name Ball No. Type Description Mux EBGA TEPBGA VPD7 AJ6 G31 I Video Port Data. The data is input from the CCIR-656 video decoder. --- VPD6 AJ7 H28 --- VPD5 AL6 H29 --- VPD4 AH8 H30 --- VPD3 AL7 H31 --- VPD2 AJ8 J28 --- VPD1 AK8 J29 --- VPD0 AH9 J30 --- VPCKIN AH7 F31 I Video Port Clock Input. The clock input from the video decoder. --- |
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