SC3200 datasheet(72/447 Pages) AMD

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AMD Geode™ SC3200 Processor Data Book

Signal Definitions

Revision 5.1

SERR#

I/O

System Error. SERR# can be asserted by

any agent for reporting errors other than PCI

parity. When the PFS bit is enabled in the

GX1 module’s PCI Control Function 2 regis-

ter (Index 41h[5]), SERR# is asserted upon

assertion of PERR#.

This signal is internally connected to a pull-

up resistor.

---

REQ1#

Request Lines. REQ[1:0]# indicate to the

arbiter that an agent requires the bus. Each

master has its own REQ# line. REQ# priori-

ties (in order) are:

VIP

IDE Channel 0

IDE Channel 1

Audio

USB

External REQ0#

External REQ1#.

Each REQ# is internally connected to a pull-

up resistor.

---

REQ0#

---

GNT1#

Grant Lines. GNT[1:0]# indicate to the

requesting master that it has been granted

access to the bus. Each master has its own

GNT# line. GNT# can be retracted at any

time a higher REQ# is received or if the mas-

ter does not begin a cycle within a minimum

period of time (16 PCI clocks).

Each of these signals is internally connected

to a pull-up resistor.

GNT0# must have a pull-up resistor of 1.5

Ω and GNT1# must have a pull-up resistor

of 1.5 K

Ω.

DID1 (Strap)

GNT0#

DID0 (Strap)

3.4.6

PCI Bus Interface Signals (Continued)

Signal Name

BalL No.

Type

Description

Mux

EBGA

TEPBGA

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