SC3200 datasheet(382/447 Pages) AMD

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382

AMD Geode™ SC3200 Processor Data Book

Electrical Specifications

Revision 5.1

Table 9-12. Memory Controller Timing Parameters

Symbol

Parameter

Min

Max

Unit

Comments

Control output valid from SDCLK[3:0]

-3.0 + (x * y)

0.1 + (x * y)

Note 1, Note 2

MA[12:0], BA[1.0] output valid from

SDCLK[3:0]

-3.2 + (x * y)

0.1 + (x * y)

Note 2

MD[63.0] output valid from SDCLK[3:0]

-2.2 + (x * y)

0.7 + (x * y)

Note 2

MD[63.0] read data in setup to SDCLK_IN

1.3

MD[63:0] read data hold to SDCLK_IN

2.0

SDCLK[3:0], SDCLK_OUT cycle time

233 MHz

266 MHz

8.3

13.5

SDCLK[3:0], SDCLK_OUT fall/rise time

between (VOLD-VOHD)

2ns

SDCLK_IN fall/rise time between

(VILD-VIHD)

2ns

t10

SDCLK[3:0], SDCLK_OUT high time

233 MHz

4.0

266 MHz

3.0

t11

SDCLK[3:0], SDCLK_OUT low time

233 MHz

4.0

266 MHz

2.5

Note 1. Control output includes all the following signals: RASA#, CASA#, WEA#, CKEA, DQM[7:0], and CS[1:0]#.

Load = 50 pF, VCORE = 1.8V@ 233/266 MHz, VIO = 3.3V, @25

oC.

Note 2. Use the Min/Max equations [value+(x * y)] to calculate the actual output value.

x is the shift value which is applied to the SHFTSDCLK field, and y is 0.45 the core clock period.

Note that the SHFTSDCLK field = GX_BASE+Memory Offset 8404h[5:3]. Refer to the AMD Geode™ GX1 Proces-

sor Data Book for more information.

For example, for a 266 MHz SC3200 running a 88.7 MHz SDRAM clock, with a shift value of 3:

t1 Min = -3 + (3 * (3.76 * 0.45)) = 2.08 ns

t1 Max = 0.1 + (3 * (3.76 * 0.45)) = 5.18 ns

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