SC3200 datasheet(435/447 Pages) AMD

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AMD Geode™ SC3200 Processor Data Book

435

Electrical Specifications

Revision 5.1

Figure 9-56. Power-Up Sequencing Without PWRBTN# Timing Diagram

ACPI is non-functional and all ACPI outputs are undefined when the power-up sequence does not include using the power

button. SUSP# is an internal signal generated from the ACPI block. Without an ACPI reset, SUSP# can be permanently

asserted. If the USE_SUSP bit in CCR2 of GX1 module is enabled (Index C2h[7] = 1), the CPU will stop.

If ACPI functionality is desired, or the situation described above avoided, the power button must be toggled. This can be

done externally or internally. GPIO63 is internally connected to PWRBTN#. To toggle the power button with software,

GPIO63 must be programmed as an output using the normal GPIO programming protocol (see Section 6.4.1.1 "GPIO Sup-

port Registers" on page 240). GPIO63 must be pulsed low for at least 16 ms and not more than 4 sec.

Asserting POR# has no effect on ACPI. If POR# is asserted and ACPI was active prior to POR#, then ACPI will remain

active after POR#. Therefore, BIOS must ensure that ACPI is inactive before GPIO63 is pulsed low.

Table 9-44. Power-Up Sequence Not Using the Power Button Timing Parameters

Symbol

Parameter

Min

Max

Unit

Comments

Voltage sequence

-100

100

Optimum power-up results with

t1 = 0.

POR# inactive after VSBL, VCORE, VSB,

and VIO applied

POR# must not glitch during

active time.

32KHZ startup time

Time required for 32 KHz oscilla-

tor and 14.318 MHz derived from

PLL6 to become stable at which

time the RTC can reliably count.

VSBL, VCORE

VSB, VIO

POR#

VSBL and VCORE should be tied together.

VSB and VIO should be tied together.

32KHZ

SC3200 Datasheet(PDF) 435 Page - Advanced Micro Devices