SC3200 datasheet(115/447 Pages) AMD

115 / 447 page

AMD Geode™ SC3200 Processor Data Book

115

SuperI/O Module

Revision 5.1

Table 5-7. RTC Configuration Registers

Bit

Description

Index F0h

RAM Lock Register - RLR (R/W)

When any non-reserved bit in this register is set to 1, it can be cleared only by hardware reset.

Block Standard RAM.

0: No effect on Standard RAM access. (Default)

1: Read and write to locations 38h-3Fh of the Standard RAM are blocked, writes ignored, and reads return FFh.

Block RAM Write.

0: No effect on RAM access. (Default)

1: Writes to RAM (Standard and Extended) are ignored.

Block Extended RAM Write. This bit controls writes to bytes 00h-1Fh of the Extended RAM.

0: No effect on the Extended RAM access. (Default)

1: Writes to bytes 00h-1Fh of the Extended RAM are ignored.

Block Extended RAM Read. This bit controls read from bytes 00h-1Fh of the Extended RAM.

0: No effect on Extended RAM access. (Default)

1: Reads to bytes 00h-1Fh of the Extended RAM are ignored.

Block Extended RAM. This bit controls access to the Extended RAM 128 bytes.

0: No effect on Extended RAM access. (Default)

1: Read and write to the Extended RAM are blocked: writes are ignored and reads return FFh.

2:0

Reserved.

Index F1h

Date Of Month Alarm Register Offset Register - DOMAO (R/W)

Reserved.

6:0

Date of Month Alarm Register Offset Value.

Index F2h

Month Alarm Register Offset Register - MANAO (R/W)

Reserved.

6:0

Month Alarm Register Offset Value.

Index F3h

Century Register Offset Register - CENO (R/W)

Reserved.

6:0

Century Register Offset Value.

SC3200 Datasheet(PDF) 115 Page - Advanced Micro Devices

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