LTM4663 datasheet(12/30 Pages) AD

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LT8722

Rev. 0

For more information www.analog.com

OPERATION

The LT8722 is a monolithic, fixed-frequency, current-mode,

full bridge DC/DC converter. Utilizing a hybrid drive system,

where one side of the load employs a linear drive (LDR)

while the other side of the load employs a traditional PWM

switching drive (SFB). Due to this unique architecture,

only a single inductor and output capacitor are required

to achieve traditional full bridge drive capability.

The LT8722 comes equipped with a serial peripheral inter-

face (SPI). Using the SPI, a 25-bit digital control word can

be applied to the LT8722 to achieve a desired voltage at

the converter output. Additional digital control informa-

tion can be sent and received through the SPI to achieve

the desired current limits, power limits as well as read

back device status information. Setting the switching fre-

quency of the LT8722 is also accomplished with sending

of SPI commands. Alternatively, an external clock can be

applied to the SYNC pin forcing the switching regulator

drive to operate at the externally applied clock frequency.

If the EN pin is low and the ENABLE_REQ control bit is

low, the LT8722 is shut down and draws ~15μA from the

input. When the EN pin is above 0.74V or the ENABLE_

REQ control bit is set high, the LT8722 will become pow-

ered on waiting for additional SPI commands to operate

begin switching. When driving the SWEN pin above 1.25V

and setting the SWEN_REQ control bit high, the LT8722

will begin a switching start-up sequence further detailed

in the Applications Information section of this document.

Electrical efficiency for the LT8722 is given by Equation 1.

Electrical Efficiency = 100% •

Electrical Power Delivered to LT8722 VOUT Load

LT8722 Electrical Input Power

(1)

To improve efficiency across all loads, supply current to

the internal circuitry can be sourced through the VCC pin

by reducing the VCC voltage output to 3.1V via SPI control

and overdriving VCC with 3.3V to 5.5V. Otherwise, the

VCC voltage should be programmed to 3.4V and internal

circuity will draw current directly from VIN.

The use of the analog output telemetry (AOUT) pin on the

LT8722 is optional. This output pin can be used in con-

junction with an external ADC to obtain information about

various aspects of the LT8722 operation including VIN,

VLOAD, ILOAD, die temp, etc. These outputs and their scal-

ing equations are included in the Applications Information

section of this document.

ENABLE AND STARTUP SEQUENCE

The LT8722 is in shutdown mode with ultralow quiescent

current when both the EN pin is low and the ENABLE_REQ

by either pulling the EN pin high or by setting the ENABLE_

REQ bit high through the SPI. The rising threshold of the

EN pin comparator is 0.74V with 30mV of hysteresis.

To enable the linear driver, the SPIS_STATUS register

must be cleared. This is done by writing all SPIS_STATUS

registers to a value of 0. The output current monitoring

circuitry and integrated charge pump, which powers the

linear power stage’s top MOSFET, are enabled when the

ENABLE_REQ bit is high. Clearing the latched CP_UVLO

bit is required to enable the linear power driver.

Finally, the PWM driver is enabled by applying a logic high

voltage to the SWEN pin (through a series 20k, or greater,

resistor) and writing the SWEN_REQ register to a 1.

During LT8722 start-up, large inrush currents can occur.

Using proper SPI commands and wait times, a software

controlled soft-start function can be synthesized that

keeps inrush current to a minimum. The following state-

ments encompass the recommended start-up sequence:

• First, apply proper VIN and VDDIO voltages to the LT8722.

• Second, enable the VCC LDO and other LT8722 circuitry

by raising the EN pin above the 0.74V threshold and

writing the ENABLE_REQ bit to a 1.

• Third, configure the output voltage control DAC (SPIS_

DAC) to 0xFF000000. This code will force the LDR pin

to GND when the linear power stage is later enabled.

• Fourth, write all SPIS_STATUS registers to 0. This

clears all faults and allows the linear power stage to

be enabled. Due to the actions in the prior step, when

the linear power stage turns on in this step, the output

load will be discharged to GND. Pause between this

step and the next for ~1ms to allow any prebiased out-

put condition to dissipate.

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