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LTM4663 Datasheet(PDF) 13 Page - Analog Devices

Part # LTM4663
Description  Ultracompact 4A, 15V, Full Bridge Driver with SPI
PDF  30 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM4663 Datasheet(HTML) 13 Page - Analog Devices

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LT8722
13
For more information www.analog.com
Rev. 0
• Fifth, ramp the output voltage control DAC (SPIS_DAC)
from code 0xFF000000 to code 0x00000000 in a con-
trolled manner so that the linear driver output (LDR)
ramps from GND to VIN/2. During this ramping period,
both the PWM driver output (SFB) and linear driver
output (LDR) move together to VIN/2. The ramp time
for this controlled movement to VIN/2 should be a mini-
mum of 5ms.
• Sixth, enable the PWM switching behavior by raising
the SWEN pin above the 1.25V threshold and writing
the SWEN_REQ bit to a 1. With both output terminals
at VIN/2, the inrush current through the output load
is greatly minimized. After the PWM driver switching
activity is enabled, keep the output voltage control DAC
(SPIS_DAC) code unchanged for a minimum of 160μs.
• Finally, the output voltage control DAC (SPIS_DAC)
code can be stepped in a controlled manner to the
desired code. The LDR and SFB outputs will begin to
diverge from one another until the desired differential
voltage is developed across the output load, the differ-
ential output voltage reaches the preset voltage limit,
or the output current reaches the preset current limit.
Figure 2 shows the flow chart of the enable sequence and
Figure 3 shows an example of the soft-start profile where
the instruction about soft-start guidance is followed.
NO
BOOTSTRAP CAP
VOLTAGE REFRESH
EN PIN > 0.74V?
SUCCESSFULLY CLEAR
SPIS_STATUS
FAULT REGISTERS
VCC
REGULATOR ON
ENABLE_REQ = 1?
YES
NO
LINEAR OUTPUT
ENABLED
YES
NO
YES
VIN AND VDDIO UP
8722 F02
VSFB AND VLDR
DIVERGE CONTROLLED
BY VDAC
ENABLE_REQ = 1?
AND SWEN > 1.125V
AND SWEN_REQ = 1?
LINEAR OUTPUT
STARTS CONTROLLED
BY VDAC
Figure 2. Flow Chart of Start-Up Sequence
1/2 VIN
8722 F03
VSFB
VLDR
VSFB FOLLOWS VLDR
VOUT BUILDS UP
Figure 3. Soft-Start Profile in Cooling Mode
POWERING THE DRIVERS
The LT8722 operates at an input voltage range of 3.1V to
15V that is applied to the VIN pin and an input range of
2.7V to 6V that is applied to the VDDIO pin.
The VIN pin is the power supply for the PWM driver and
the linear power driver. When configuring the power sup-
ply to the VIN pin keep in mind that, at high current loads,
the input voltage may drop substantially due to a voltage
drop in the wires between the front end power supply and
the VIN pin. Leave a proper voltage margin when design-
ing the front-end power supply to maintain good perfor-
mance. Minimize the trace length from the power supply
to the VIN pin to help mitigate the voltage drop.
SETTING THE SWITCHING FREQUENCY
The LT8722 uses a constant frequency PWM architec-
ture that can be programmed to switch from 500kHz to
3MHz through the SW_FRQ_SET register bits and further
be adjusted by ±15% through the SW_FRQ_ADJ regis-
ter bits. Table 1 and Table 2 show the frequency setup
summary.
Table 1. Switching Frequency Configuration
SW_FRQ_SET BITS
SWITCHING FREQUENCY
000
500kHz
001
1MHz
010
1.5MHz
011
2MHz
100
2.5MHz
101, 110, 11
3.0MHz
OPERATION



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