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LTM4663 Datasheet(PDF) 22 Page - Analog Devices

Part # LTM4663
Description  Ultracompact 4A, 15V, Full Bridge Driver with SPI
PDF  30 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM4663 Datasheet(HTML) 22 Page - Analog Devices

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LT8722
22
Rev. 0
For more information www.analog.com
SPIS_COMMAND Register
This register is used to enable and disable the device,
set the switching frequency, control the PWM output
duty cycle, set the VCC voltage, set initial peak inductor
SPI REGISTER DESCRIPTIONS
current, execute the software reset and set the linear
driver’s power loss regulation threshold.
BITS
SYMBOL
OPERATION
B[0]
ENABLE_REQ
VCC LDO enable bit and linear power stage enable request bit. Default: 0x0
VCC LDO is enabled when ENABLE_REQ = 1 OR the EN pin is high.
Linear power stage is enabled when ENABLE_REQ = 1 and the SPIS_STATUS fault bits are cleared.
B[1]
SWEN_REQ
PWM switch enable request bit. Default: 0x0
1b1: Request PWM switching enable. PWM switching is enabled when SWEN_REQ = 1 and the SWEN pin is high
and the VCC LDO is enabled.
1b0: PWM switching is disabled.
B[4:2]
SW_FRQ_SET[2:0] PWM switch frequency control bits. Default: 0x5
3b000: 0.5MHz
3b001: 1MHz
3b010: 1.5MHz
3b011: 2MHz
3b100: 2.5MHz
3b101, 3b110, 3b111: 3MHz
B[6:5]
SW_FRQ_ADJ[1:0] PWM switch frequency adjustment bits. Default: 0x0
2b00: 0%
2b01: +15%
2b10: –15%
2b11: 0%
B[8:7]
SYS_DC[1:0]
PWM duty cycle control bits. Default: 0x0
2b00: 20%–80% duty cycle
2b01: 15%–85% duty cycle
2b10, 2b11: 10%–90% duty cycle



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