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LTM4663 Datasheet(PDF) 23 Page - Analog Devices

Part # LTM4663
Description  Ultracompact 4A, 15V, Full Bridge Driver with SPI
PDF  30 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM4663 Datasheet(HTML) 23 Page - Analog Devices

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Rev. 0
BITS
SYMBOL
OPERATION
B[9]
VCC_VREG
VCC LDO regulation control bit. Default: 0x1
1b1: VCC LDO regulation voltage = 3.4V
1b0: VCC LDO regulation voltage = 3.1V
B[10]
Unused
Must always be set to 0x0
B[13:11]
SW_VC_INT[2:0]
Typical peak inductor current after BST–SW refresh period control bits. Default: 0x2
3b000: 0.252A
3b001: 0.594A
3b010: 0.936A
3b011: 1.278A
3b100: 1.620A
3b101: 1.962A
3b110: 2.304A
3b111: 2.646A
B[14]
SPI_RST
Software reset request bit. Default: 0x0 (Active High)
This register bit (write “1” to this register bit) is used to manually reset all registers (except SPIS_STATUS register)
to default values
B[18:15]
PWR_LIM[3:0]
Linear power stage MOSFET power limit control bits. Default: 0x5
4b0000: 2W
4b0101: No Limit
4b1010: 3W
4b1111: 3.5W
Other bit combinations not allowed.
B[31:19]
–
Ignored
SPIS_STATUS REGISTER
This register is used to store PWM out switching status,
output current limit loop status, linear power loss regula-
tion status, PWM output duty status, software reset event
status, output over current failure status, overtemperature
SPI REGISTER DESCRIPTIONS
failure status, VCC UVLO failure status, VDDIO UVLO fail-
ure status, internal charge pump UVLO failure status and
internal 2.5V voltage reference UVLO failure status.
BITS
SYMBOL
OPERATION
B[0]
SWEN
Real-time PWM switching status indicator bit. Default: 0x0
1b1: PWM switching enabled
1b0: PWM switching disabled
B[1]
SRVO_ILIM
Real-time current limit loop status indicator bit. Default: 0x0
1b1: Operating in current limit loop
1b0: Not operating in current limit loop
B[2]
SRVO_PLIM
Real-time linear power stage bottom MOSFET and top MOSFET power limit loop status indicator bit. Default: 0x0
1b1: Operating in power limit loop
1b0: Not operating in power limit loop
B[3]
MIN_OT
Real-time PWM duty cycle status indicator bit. Default: 0x0
1b1: Operating in min or max duty cycle,
1b0: Not operating in min or max duty cycle.
B[4]
POR_OCC
Latched soft reset event status indicator bit. Default: 0x0
1b1: Soft reset event by SPI_RST bit or hard reset by faults happened since last cleared
1b0: Soft reset event by SPI_RST bit has not happened since last cleared



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