LTM4663 datasheet(14/30 Pages) AD

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LT8722

Rev. 0

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Table 2. Switching Frequency Adjustment

SW_FRQ_ADJ BITS

CHANGE FROM NOMINAL

+15%

–15%

The operating frequency of the LT8722 PWM buck

driver can also be synchronized to an external source

automatically.

To synchronize to the external source, simply provide a digi-

tal clock signal into the SYNC pin and the LT8722 will oper-

ate at the SYNC clock frequency. The duty cycle of the SYNC

clock must be between 20% and 80% for proper operation.

And the SYNC frequency can always be higher than the free-

running oscillator frequency but should not be less than 30%

of the configured free-running oscillator frequency.

Selection of the operating frequency is a trade-off between

efficiency, component size and PWM duty cycle range.

The advantage of high frequency operation is that lower

value and smaller size inductors and capacitors can be

used. The disadvantages are lower efficiency and nar-

rower duty cycle range as required by the min-on time

and min-off time of the PWM driver.

BOOTSTRAP CIRCUITRY AND REFRESH PERIOD

The LT8722 integrates the bootstrap regulator to pro-

vide gate drive voltage for the top MOSFET of the PWM

driver (M3). The regulator generates a bootstrap voltage

between the BST pin and the SW pin, which is equal to

the VCC voltage.

It is recommended that an X7R or an X5R, 0.1µF ceramic

capacitor is placed between the BST pin and the SW pin.

Immediately after enabling the PWM driver, the bootstrap

capacitor voltage may not be high enough to drive the

M3 gate. A total of 32 refresh cycles, with 5μs period, are

required to charge the bootstrap capacitor before the PWM

driver starts to work properly. During each refresh cycle,

the M3 MOSFET is designed to be turned on first for 80ns

(typ), and then the M4 MOSFET is turned on for 160ns

(typ). After that, both the top and bottom MOSFETs are

turned off for the rest of the refresh cycle. By doing this, the

inrush load current is minimized. Figure 4 shows the typical

waveforms during the bootstrap cap voltage refresh period.

8722 F04

TOP MOSFET

BOT MOSFET

INDUCTOR

CURRENT

80ns

160ns

5 s

32 CYCLES IN TOTAL

Figure 4. Bootstrap Capacitor Voltage Refresh Cycles

VCC LDO REGULATOR

An internal low dropout (LDO) regulator produces a 3.4V

supply to the VCC pin from VIN when the VCC_VREG reg-

ister bit is 1. This LDO can supply enough current for

the LT8722’s circuitry and must be bypassed to ground

with a minimum 1µF ceramic capacitor. This bypassing is

necessary to supply the high transient currents required

by the PWM power MOSFET drivers.

To improve overall efficiency, an external supply between

3.4V to 3.8V can be applied to the VCC pin. When an exter-

nal supply is used, the VCC_VREG register bit needs to be

configured to 0. With this setting, the VCC LDO’s regula-

tion voltage will be reduced to 3.1V. The VCC pin can then

be overdriven with an external supply between 3.4V and

3.8V. Because the VCC target output voltage is 3.1V and

because the VCC LDO can only source current, only the

external supply will control the VCC pin in this situation.

SETTING INITIAL PEAK INDUCTOR CURRENT

When the PWM driver is enabled, the initial peak inductor

current can cause some transient behavior to the output

voltage and current for a short period of time. The optimal

initial peak inductor current is different for different VIN,

switching frequency and inductor values. The SW_VC_INT

Table 3 shows the configuration summary. When the rec-

ommended startup sequence is followed, the optimal initial

peak inductor current can be calculated with Equation 2.

IPEAK_INIT =

VIN

4 • L • fSW

(2)

OPERATION

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