LTM4663 datasheet(17/30 Pages) AD

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LT8722

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Rev. 0

PWM DUTY CYCLE CONFIGURATION

The minimum and maximum output voltage can be

achieved at operating points A and D as shown in Figure 7.

At the operating point labeled A, the PWM driver is oper-

ating with a minimum on-time (tON,MIN) of 50ns (typ).

If the PWM driver is commanded by the output voltage

control DAC to output a voltage at the SFB pin that violates

the minimum on-time, the PWM driver may begin pulse-

skipping to achieve the desired output voltage. It’s recom-

mended to avoid these extreme operating points as the

output voltage regulation may begin to degrade. Similarly,

at the operating point labeled D, the PWM driver is oper-

ating with a minimum off-time (tOFF,MIN) of 50ns (typ).

If the PWM driver is commanded by the output voltage

control DAC to output a voltage that violates the minimum

off-time, the PWM driver may begin pulse-skipping to

achieve the desired output voltage. It’s recommended to

avoid these extreme operating points as the output volt-

age regulation may begin to degrade.

For a given switching frequency, operating points labeled

B and C need to be considered carefully to avoid tON,MIN

and tOFF,MIN violations. As an example, using a switching

frequency of 3MHz, the typical tON,MIN and tOFF,MIN are

both 50ns. From this information, it can be calculated

that the minimum and maximum operating duty cycle that

can be tolerated by the PWM driver are 15% and 85%,

respectively. Thus, the selected duty cycle range configu-

ration, set by the SYS_DC register, should be within this

range. According to Table 6, the SYS_DC register should

be configured as [0,0].

Table 6. Duty Cycle Configuration

SYS_DC BITS

DUTY CYCLE RANGE

DUTY_CYCLE_MAX

20~80%

0.2

15~85%

0.15

10, 11

10~90%

0.1

For a given VIN voltage and a switching frequency, the

maximum achievable output voltage is decided by the

minimum and maximum duty cycles. As an example,

assuming VIN = 8V and a switching frequency of 3MHz,

the output voltage range is approximately –6.8V to +6.8V

when excluding the small voltage drops across the mono-

lithic power MOSFETs.

MAXIMUM TEC VOLTAGE LIMITS

The maximum positive and negative TEC voltages are set

in the SPIS_OV_CLAMP and SPIS_UV_CLAMP registers

respectively. These two registers set the maximum and

minimum SPIS_DAC register values and, in turn, set the

maximum positive and negative TEC voltages. Table 7 and

Table 8 show how the SPIS_DAC register value is limited

by SPIS_OV_CLAMP register and the SPIS_UV_CLAMP

Table 7. Max SPIS_DAC vs SPIS_OV_CLAMP

SPIS_OV_CLAMP BITS

MAX SPIS_DAC VALUE

4b0000

0x000FFFFF

4b0001

0x001FFFFF

• • •

4b1110

0x00EFFFFF

4b1111

0x00FFFFFF

Table 8. Min SPIS_DAC vs SPIS_UV_CLAMP

SPIS_OV_CLAMP BITS

MIN SPIS_DAC VALUE

4b0000

0xFF000000

4b0001

0xFF100000

• • •

4b1110

0xFFE00000

4b1111

0xFFF00000

OUTPUT CURRENT LIMITS

To protect the load, the LT8722 integrates two 9-bit DACs

to limit the maximum output currents in both directions

independently. Positive current refers to current flow-

ing from LDR to SFB. The current limits can be set in

the SPIS_DAC_ILIMP and SPIS_DAC_ILIMN registers.

The current limits can be calculated with Equation 9

and Equation 10.

ILIMP = 6.8A − (SPIS_DAC_ILIMP • 13.28mA) (9)

where SPIS_DAC_ILIMP is 0 to 462.

ILIMN = SPIS_DAC_ILIMN • − 13.28mA

(10)

where SPIS_DAC_ILIMN is 48 to 511.

The two 9-bit DACs provide wide output current limit

settings. When the output voltage is limited by ILIMP or

ILIMN, and the PWM driver reaches the min-on or min-off

OPERATION

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