LTM4663 datasheet(20/30 Pages) AD

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LT8722

Rev. 0

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SERIAL PERIPHERAL INTERFACE

The LT8722 utilizes an SPI slave to communicate with

an external microcontroller. Through SPI, the master can

configure the LT8722 functions and set parameters. The

master can also read back the status of the LT8722.

The LT8722 SPI is a full duplex protocol on 4-signal lines.

A clock named SCK is sent from the master to synchronize

MOSI and MISO data. A chip-select enable bar signal (active

low) named CS is sent from the master to enable LT8722

SPI communication. A unidirectional data line named MOSI

is sent from the master to the LT8722 and a unidirectional

data line named MISO is driven from the LT8722 to the

master. Bits are always sent or driven MSB first. SPI Mode

0 is supported in the LT8722. In Mode 0, the SCK is low

when the clock is inactive, and bits are always sampled at

the rising edge of SCK and driven at the falling edge of SCK.

SPI: Packet Format

A packet is a fundamental data element composed of indi-

vidual bits encoding the command, address and/or data

accompanied by a CRC/ACK. Different packet types con-

tain different numbers of bits. There are 3 types of packets

for the LT8722 SPI: Status Acquisition, Data Write, and

Data Read.

Each packet accomplishes one complete transaction over

the interface, whether a Status Acquisition, Data Write,

or Data Read. Packets are always initiated by pulling CS

down and always end by pulling CS up.

8722 F12

MOSI

C[7:0]

A[7:0]

ACK[7:0]

00000 STATUS[10:0] CRC[7:0]

MISO

CRC[7:0]

0xXX

Figure 12. Status Acquisition Packet

8722 F13

MOSI

C[7:0]

A[7:0]

CRC[7:0]

0xXX

00000 STATUS[10:0] CRC[7:0]

ACK[7:0]

MISO

0xXX

D[31:24]

D[23:16]

D[15:8]

D[7:0]

Figure 13. Data Write Packet

SPI ARCHITECTURE

8722 F14

MOSI

C[7:0]

A[7:0]

0xXX

D[23:16]

00000 STATUS[10:0]

D[31:24]

ACK[7:0]

MISO

D[15:18]

D[7:0]

CRC[7:0]

0xXX

CRC[7:0]

0xXX

Figure 14. Data Read Packet

SPI: Command

C[7:0] is an 8-bit field indicating the action that the master

wants to perform as shown in Table 13.

Table 13. Command Byte Description

NAME

C[7:0]

DESCRIPTION

0x00

Status Acquisition Command

0x02

Data Write Command

0x04

Data Read Command

SPI: ADDRESS

A[7:0] is an 8-bit field indicating the register address

that the master wants to access. Table 14 is the register

address summary and the address field duration is 8-SCK

cycles. A[0] is always zero.

Table 14. Address Description, A[0] Is Always Zero

ADDRESS, A[7:1]

0x00

SPIS_COMMAND

0x01

SPIS_STATUS

0x02

SPIS_DAC_ILIMN

0x03

SPIS_DAC_ILIMP

0x04

SPIS_DAC

0x05

SPIS_OV_CLAMP

0x06

SPIS_UV_CLAMP

0x07

SPIS_AMUX

SPI: DATA

D[31:0] is a 4-byte field containing the data to transfer.

The data field duration is 32-SCK cycles.

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