LTC4413 datasheet(21/32 Pages) AD

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LTC4421

Rev. 0

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takes a correspondingly longer time to charge up by the

internal charge pump, resulting in longer delays from ini-

tial power-up of the first input supply to first connection

to the output. A smaller capacitor suffers more voltage

drop during a channel turn-on event as it shares charge

with CG and the MOSFET CISS capacitances. Given the

limited charging capability of the charge pump, continu-

ously changing channels at rates higher than 80Hz (typi-

cal) eventually depletes the CCPO capacitor, causing dis-

connection of both inputs from the output. At that point,

the charge pump charges the CCPO capacitor above 6.7V,

the inputs are then allowed to reconnect to the output, and

the process repeats.

Analog Current Limit Loop Stability

The active current limit loop is compensated by adding a

capacitor CG between the gate and source of the external

MOSFETs. Choosing 47nF for CG ensures stability for all

recommended MOSFETs. In addition, add a snubber from

the input supply to ground consisting of resistor RSN in

series with capacitor CSN. Choose RSN using Equation 16.

SN =

LIM

(16)

where VIN is the maximum input supply voltage and ILIM

is the current limit being set by RSENSE. Setting CSN to

10µF works well for all applications. Applications having

small input inductance and low output load current may

use values as low as 1µF for CSN.

Setting Qualification Time for Validity

The QUAL pin sets the amount of time a supply must

be inside the OV, UV voltage window to be valid.

Connect a capacitor CQUAL from QUAL to ground and

use Equation 17 to set the validation time:

VALID = CQUAL

• 16[ms/nF]

(17)

where tVALID is the validation time. Note that the validation

time is the same for both channels. To set a fixed qualifi-

cation time of 3.5µs, connect QUAL to INTVCC instead of

connecting a capacitor to ground.

APPLICATIONS INFORMATION

If possible, set a qualification time on the order of 10ms

or longer. This allows the LTC4421’s gate driver parking

circuitry to pre-bias the GATE1 voltage to its GATE Parking

Voltage when hot-plugging the V1 input supply. This will

reduce switchover time and hence output voltage droop

when switching from Channel 2 to Channel 1.

Optional Charge Pump Pre-Charge Circuit

The LTC4421 prevents the input supplies from being

validated and powering the output until the external CCPO

capacitor voltage is charged to 6.7V (VCPO(UVL)) above the

higher of the CPOREF and INTVCC voltages. With a typical

CCPO capacitor of 1µF, the charge pump voltage may take

several hundred milliseconds to charge to 6.7V. For input

supplies ≥ 12V, this time can be shortened by pre-charging

the CPO pin with the circuit shown in Figure 9. The 12V

Zener diode Z1 and NPN transistor Q1 are used to quickly

charge the CPO voltage to about 10.8V above ground. For

V1, V2 voltages below 12V, the circuit pre-charges CPO

to a voltage approximately 1.8V below the higher of the

V1 and V2 voltages. Diode D3 prevents reverse current

conduction when an input supply is connected to VOUT

and causes the CPO voltage to rise above 9V. Diodes D1

and D2 form a diode-OR circuit that powers the Z1 and Q1

from the higher of the V1 and V2 input supply voltages.

Figure 9. Optional CPO Pre-Charge. The Higher Voltage of Input

Supplies V1 and V2 Pre-Charges the CPO Voltage to Reduce

System Power-Up Time

CPO

CPOREF

CCPO

1µF

12V

BZX84C12L

1N4148

COUT

220µF

1N4148

100k

1N4148

2N2222

VOUT

LTC4421

LTC4421 F09

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