LTC4413 datasheet(27/32 Pages) AD

27 / 32 page

LTC4421

Rev. 0

For more information www.analog.com

Preventing Input Hold-Up During Unplug Events

Figure 16 includes a backplane connector with a kelvin

sense. The resistive divider network that sets the OV

and UV thresholds is connected to the kelvin sense.

Disconnecting the supply powering V1 causes a nearly

immediate UV fault, because there is no hold-up capaci-

tance on the OV1, UVF1 or UVR1 pins. The output volt-

age discharges minimally before the UV fault occurs, as

the output discharge rate is very slow compared to the

UV fault time. Without a kelvin sense connection, upon

input supply disconnection the resistive divider would

stay connected to the drain of M1. The output, OV1, UVF1

and UVR1 pin voltages would all fall at the rate dictated

by the output discharge, and the channel would not be

disconnected until the output voltage dropped below the

UVF1 threshold voltage.

APPLICATIONS INFORMATION

SOA Doubler

Multiple LTC4421’s can be used to control parallel MOSFET

pathwaysfromeachinputtotheoutput,asshowninFigure 17.

This is valuable in very high current applications to cut the

SOA and load current carrying burdens of each MOSFET in

half. LTC4421 #1 acts as a master and performs all monitor-

ing functions, including OV, UV, fault and reverse current. After

LTC4421 #2 drives the VALID12 and VALID22 signals low to

indicate that it has successfully powered up, it acts as a slave

to LTC4421 #1, turning its external MOSFETs on and off at

LTC4421 #1’s command. Connecting LTC4421 #1’s CH1 and

CH2 outputs through inverters U3 and U4 to LTC4421 #2’s

DISABLE1 and DISABLE2 inputs, respectively, synchronizes

channel turn-on and turn-off of the two LTC4421’s. NOR gates

U1 and U2 prevent LTC4421 #1 from turning on its MOSFETs

until LTC4421 #2’s inputs are validated. This ensures that

LTC4421 #1 never turns on its MOSFETs when LTC4421 #2

is unable to turn on its MOSFETs.

Figure 15. Recommended 2-Layer PCB Layout

GATE1

UVF1

UVR1

UVR2

UVF2

GATE2

SOURCE1

SOURCE2

FROM V1

INPUT SOURCE

TMR1

DISABLE1

CH1

VALID1

OV1

VALID2

CH2

DISABLE2

TMR2

OV2

RSENSE1

RSN1

CSN1

RSN2

CSN2

0.03" PER

AMPERE

TRANSIENT

VOLTAGE

SUPPRESSOR

CCPO

CTMR1

CINTVCC

GND

LTC4421 F15

NOT TO SCALE

FROM V2

INPUT SOURCE

RSENSE2

0.03" PER

AMPERE

TRANSIENT

VOLTAGE

SUPPRESSOR

CTMR2

Layer 1

Layer 2

VOUT

METAL

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