AS3911 datasheet(49/159 Pages) AMSCO

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ams Datasheet

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[v2-11] 2016-Jun-13

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AS3911 − Application Information

After data reception is terminated the external microcontroller

needs to know how much data is still stored in the FIFO: This

information is available in the FIFO Status Register 1 and FIFO

Status Register 2 which displays number of bytes in the FIFO

which were not read out. FIFO Status Register 1 can also be read

while reception and transmission processes are active to get

info about current number of bytes in FIFO. In that case user

has to take in account that Rx/Tx process is going on and that

the number of data bytes in FIFO may have already changed by

the time the reading of register is finished.

The FIFO Status Register 2 additionally contains two bits which

indicate that the FIFO was not correctly served during reception

or transmission process (FIFO overflow and FIFO underflow).

FIFO overflow is set when too much data is written in FIFO. In

case this bit is set during reception the external controller did

not react on time on water level IRQ and more than 96 bytes

were written in the FIFO. The received data is of course

corrupted in such a case. During transmission this means that

controller has written more data than FIFO size. The data to be

transmitted was corrupted.

FIFO underflow is set when data was read from empty FIFO. In

case this bit is set during reception the external controller read

more data than was actually received. During transmission this

means that controller has failed to provide the quantity of data

defined in number of transmitted bytes registers on time.

Pin MCU_CLK

Pin MCU_CLK may be used as clock source for the external

microcontroller. Depending on the operation mode either a low

frequency clock (32 kHz) from the RC oscillator or the clock

signal derived from crystal oscillator is available on pin

MCU_CLK. The MCU_CLK output pin is controlled by bits out_c1,

out_cl0 and lf_clk_off in the IO Configuration Register 1. Bits

out_cl enable the use of pin MCU_CLK as clock source and

define the division for the case the crystal oscillator is running

(13.56MHz, 6.78MHz and 3.39MHz are available). Bit lf_clk_off

controls the use of low frequency clock (32kHz) in case the

crystal oscillator is not running. By default configuration, which

is defined at power-up, the 3.39MHz clock is selected and the

low frequency clock is enabled.

In case the Transparent mode (see Stream Mode and

Transparent Mode) is used the use of MCU_CLK is mandatory

since clock which is synchronous to the field carrier frequency

is needed to implement receive and transmit framing in the

external controller. The use of MCU_CLK is recommended also

for the case where the internal framing is used. Using MCU_CLK

as the microcontroller clock source generates noise which is

synchronous to the reader carrier frequency and is therefore

filtered out by the receiver while using some other incoherent

clock source may produce noise which perturbs the reception.

Use of MCU_CLK is also better for EMC compliance.

AS3911 Datasheet(PDF) 49 Page - ams AG

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