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PC8374L Datasheet(PDF) 201 Page - National Semiconductor (TI) |
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PC8374L Datasheet(HTML) 201 Page - National Semiconductor (TI) |
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201 / 239 page ![]() 9.0 Legacy Functional Blocks (Continued) Revision 1.1 201 www.national.com Figure 39. SP2 Register Bank Architecture Table 76 shows the main functions of the registers in each bank. Banks 0-3 control both UART and IR modes of operation; banks 4-7 control and configure the IR modes only. Table 76. Register Bank Summary The register maps in this chapter use the following abbreviations for Type: • R/W = Read/Write • R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. • W = Write • RO = Read-Only • R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Bank UART Mode IR Mode Main Functions 0 ✓✓ Global Control and Status 1 ✓✓ Legacy Bank 2 ✓✓ Alternative Baud Generator Divisor, Extended Control and Status 3 ✓✓ Module Revision ID and Shadow registers 4 ✓ IR mode setup 5 ✓ IR Control 6 ✓ IR Physical Layer Configuration 7 ✓ CEIR and Optical Transceiver Configuration BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 Offset 07h Offset 06h Offset 05h Offset 04h LCR/BSR Offset 02h Offset 01h Offset 00h Common Register Throughout All Banks IR Special Banks (Banks 4-7) Winbond Electronics Corp. Advanced PC Product Center |
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