PC8374L datasheet(130/239 Pages) NSC

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8.0 Health Management (HM) (Continued)

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For Low/High Limit: Whenever the temperature data changes state, the associated ZONEn_EV bit in the HM Interrupt Status

Interrupt Enable Register 1 (see Section 8.4.6 on page 145) to create an IRQ. ZONEn_EV can also be enabled by the associ-

ated xxx_EN bit in the HM SMI/SCI Enable Register 1 (see Section 8.4.13 on page 150) to create an SMI or SCI interrupt.

For Critical Limit: Whenever the temperature data changes state, the associated CRITn_EV bit in the HM Interrupt Status

terrupt Enable Register 3 (see Section 8.4.11 on page 149) to create an IRQ. CRITn_EV can also be enabled by the associated

xxx_EN bit in the HM SMI/SCI Enable Register 3 (see Section 8.4.15 on page 152) to create an SMI or SCI interrupt.

A hysteresis of 4

°C can be applied to the limit checking by setting the TEMP_HYST bit in the Monitoring Control register

(see Section 8.5.54 on page 176) to 1.

Each of the Temperature channels can be configured as a “VDD Channel” (see Section 8.5.55 on page 177). Temperature

Zone1 is configured by default as a VDD channel. When VDD3 supply is off, all channels that are configured as VDD channels

are disabled. Monitoring for these channels is disabled and all the status bits are reset to 0, including the event bits in the

HM Interrupt Status register (see Section 8.4.4 on page 143 and Section 8.4.5). An exception is the status bits associated

with the channel critical limits (CRITn_STS), which are not reset when the VDD3 supply is off. Channels that are configured

as VDD channels are enabled 182 ms after the VDD3 supply is turned back on.

8.2.4

Voltage Monitoring

Voltage is monitored for five different voltage channels: 2.5V, Vccp (2.25V), 3.3V, 5V and 12V. The voltage data is updated

and stored as an unsigned 8-bit value in the Voltage Reading registers. The data represents a relative value. Nominal volt-

age value (2.5V for the 2.5V monitoring, 2.25V for Vccp, etc.) is represented by C0h which is 3/4 full-scale (full scale being

FFh).

The voltage data is compared with configurable low and high limits contained in the Voltage Low Limit and Voltage High

Limit registers, respectively. The data format in the limit registers is the same as in the voltage data registers.

Whenever the voltage data exceeds a limit, an xxx_ERR status bit is set in Status Register 1 and Status Register 2 (see

Section 8.5.23 on page 164 to Section 8.5.24), and an xxx_STS bit in the HM Sensor Status Register 1 and HM Sensor

Status Register 2 is set (see Section 8.4.8 on page 147 and Section 8.4.9).

Voltage data is considered to be in a “Good” state when the data does not exceed any limit. A “Fail” state is when the voltage

data exceeds a limit. Whenever the voltage data changes state, the associated xxx_EV bit in the HM Interrupt Status Reg-

ister 1 and HM Interrupt Status Register 2 is set (see Section 8.4.4 on page 143 and Section 8.4.5). xxx_EV can be enabled

to create an IRQ by the associated xxx_EN bit in the HM Interrupt Enable Register 1 and HM Interrupt Enable Register 2

(see Section 8.4.6 on page 145 and Section 8.4.7). The xxx_EV bit can also be enabled to create an SMI or SCI interrupt

by the associated xxx_EN bit in the HM SMI/SCI Enable Register 1 and HM SMI/SCI Enable Register 2 (see Section 8.4.13

on page 150 and Section 8.4.14).

A hysteresis, which is the value of the Voltage Limit register (High or Low) LSBit multiplied by 4 (see Section 8.5.54 on

page 176), can be applied to the limit checking by setting the VOLT_HYST bit in the Monitoring Control register to 1.

Each of the Voltage channels can be configured as a “VDD Channel” (see Section 8.5.55 on page 177). Vccp is configured

by default as a VDD channel. Whenever VDD3 supply is off, the channels configured as VDD channels are disabled. Monitor-

ing for these channels is disabled, and all the status bits are reset to 0, including the event bits in the HM Interrupt Status

tween 91 ms and 182 ms after the VDD3 supply is turned back on.

8.2.5

Device Enumeration and HM Channel Association

The three enumeration and HM channel association stages are done in the following order:

1. Device enumeration

2. Extended device enumeration

3. HM channel association

The ready bit in the configuration register (see Section 8.5.22 on page 163) is set to 0 (not-ready) during all three stages.

In any stage, if a SensorPath transaction fails on three successive attempts, the HM assumes a communication error with

the LMxx Sensor device occurred and proceeds accordingly (see Section 8.2.10 on page 139).

Device Enumeration

The HM, after VSB3 power-up but before it is ready to respond to attention requests, performs device enumeration to identify

the LMxx Sensor devices currently connected to the SensorPath bus.

To enumerate the LMxx Sensor devices, the HM reads the Device Number register first from device number 1 and then from

device number 2. Note that a read transaction that returns device number=0h indicates a non-existent device number.

If the device enumeration fails to detect any LMxx Sensor device connected to the SensorPath bus, the HM ignores any

attention requests generated on the SensorPath bus.

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PC8374L Datasheet(PDF) 130 Page - National Semiconductor (TI)

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